4H-SiC Trench Gate Lateral MOSFET With Dual Source Trenches for Improved Performance and Reliability

Abstract

The SiC trench gate lateral MOSFET featuring dual source trenches is proposed in this work. 2D numerical simulations by TCAD are conducted to study the performance and the reliability of the proposed structure and the conventional ones. With the trench gate, the device specific ON-resistance is reduced by more than 50% compared to that of the planar gate device. The device with proposed dual source trenches can also prevent the Pwell punch through problem that occurs in conventional lateral LMOS. As a result, a blocking voltage over 1200V can be achieved with the proposed structure. The proposed devices have two types of configurations. Compared with the configuration of double shallow trenches, the configuration of deep and shallow trenches can mitigate the curvature effect near the P+ source region by increasing the effective curvature radius. As a result, the RESURF doping and epi thickness windows are both expanded by 1.5×. Furthermore, as the deep source trenches push the electric field away from the gate trench, the off-state oxide field is effectively reduced to below 3MV/cm. Thus, the longterm reliability is substantially improved. In addition, the deep and shallow source trench configuration provides the enhanced screen effect and hence lowers the gate charge by 50%. Faster switching can be achieved with this structure.

Review of the SiC LDMOS power device

“…However, the presence of the oxide-filled trench necessitates an increase in the drift region length, resulting in a rise in R on,sp . In order to avoid the impact of the oxide-filled trench on device performance, Kong et al adopted the double trench gate technology in SiC LDMOS power devices [36] , and the device diagram is depicted in Fig. 4(b).…”