5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter

Fred, Mostert; Schinkel, D.; Groothedde, Wouter; Breems, Lucien J.; Heeswijk, R. van; Koerts, Marto-Jan; Iersel, Eric van; Daniel, Groeneveld; Holland, Gertjan van; Patrick, Zeelen; Derk-Jan, Hissink; Martin, Pos; Wielage, Paul; Fre, Jorritsma; Middelink, Marc Klein

doi:10.1109/isscc.2017.7870273

Cited by 7 publications

(2 citation statements)

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“…For filter-free digital class D power amplifiers, the errors introduced by the nonlinearity and nonideal working conditions of the power stage, especially the errors introduced by the power supply noise of the power stage, seriously affect the output performance of the power amplifier [7,8]. Although the power amplifier's power supply rejection ratio (PSRR) can theoretically reach infinity when the upper and lower half bridges of the bridge-tied-load (BTL) power stage of the power amplifier are completely matched, the power supply interference is caused by the power supply noise.…”

Section: Introductionmentioning

confidence: 99%

“…e modulation distortion (PS-IMD) is still large. In response to this problem, Donida et al [7] and Mostert et al [8] introduced the output signal of the power amplifier to the input of the power amplifier by establishing a global closedloop negative feedback loop including a digital switching signal modulator and a power stage. Precorrection is performed in the terminal or switching signal modulator to achieve the purpose of correcting the power level error, but an additional analog-to-digital converter (ADC) is required, which leads to a substantial increase in system cost.…”

Section: Introductionmentioning

confidence: 99%

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Improved Error Correction Methods for Filterless Digital Class D Audio Power Amplifier Based on FCLNF

Sun

2020

Mathematical Problems in Engineering

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Aiming at correcting the error caused by the nonlinear and power supply noise of the bridge-tied-load (BTL) power stage of the filterless digital class D power amplifier, an error correction method was proposed based on feedforward power supply noise suppression (FFPSNS) and first-order closed loop negative feedback (FCLNF) techniques. This method constructed the first-order LCLNF loop for the power stage and further reduced the impact of the power supply noise on the power amplifier output by using FFPSNS technology to introduce the power supply noise into the feedback loop at the same time. The 0.35 μm CMOS process is used for analysis and comparison in Cadence. Cadence simulation results indicate that PSRR at the power supply noise frequency of 200 Hz is improved with 36.02 dB. The power supply induced intermodulation distortion (PS-IMD) components are decreased by approximately 15.57 dB and the signal-to-noise ratio (SNR) of the power amplifier is increased by 17 dB. The total harmonic distortion + noise (THD + N) of the power amplifier is reduced to 0.02% by FCLNF + FFPSNS.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%