2010
DOI: 10.1109/jstqe.2010.2041326
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5/10-Gb/s Burst-Mode Clock and Data Recovery Based on Semiblind Oversampling for PONs: Theoretical and Experimental

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Cited by 23 publications
(9 citation statements)
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“…To understand the impact of all these factors on the BBER tests described above, we added them to the data frame presented in figure 7 as configurable parameters: one of them is the CID field (consecutive identical bits [4], basically consecutive '0's constituting the silent period between two gaps) to which a phase step is added (∆φ in degrees, 360 o =1 bit clock period) modelling the phase change between two bursts. The output power of the ONU2 was modulated by an optical attenuator (JDSU, MAP-200 mVOA-A2) to introduce a configurable dynamic range (α).…”
Section: Upstream Path Characterizationmentioning
confidence: 99%
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“…To understand the impact of all these factors on the BBER tests described above, we added them to the data frame presented in figure 7 as configurable parameters: one of them is the CID field (consecutive identical bits [4], basically consecutive '0's constituting the silent period between two gaps) to which a phase step is added (∆φ in degrees, 360 o =1 bit clock period) modelling the phase change between two bursts. The output power of the ONU2 was modulated by an optical attenuator (JDSU, MAP-200 mVOA-A2) to introduce a configurable dynamic range (α).…”
Section: Upstream Path Characterizationmentioning
confidence: 99%
“…The following sections present the impact of the abovedescribed parameters on the BBER and PLR performance of the TTC-PON system equipped with two ONUs. As the type of CDR used in the FPGA for the OLT has also an impact on the ability of the system to cope with certain parameters (essentially the phase step and the lengths of the CID and the preamble), some parameters were analyzed for two CDR architectures: one based on conventional phase-tracking CDR [4] (referred as N-CDR) and one based on oversampling CDR without phase tracking [4,5] (referred as O-CDR), with the objective to quantify their immunity to the system parameters.…”
Section: Upstream Path Characterizationmentioning
confidence: 99%
“…We have experimentally tested variants of this BM-CDR in various experimental testbeds including: (1) 20-km time-division multiplexing (TDM) gigabit Ethernet PON (GEPON) uplink at 5 Gb/s [7]; (2) 1300-km deployed fiber link spanning Montreal to Quebec City and back, at 1.25 Gb/s [8]; and (3) 7-user 20-km spectral amplitude coded optical code-division multiple access (SAC-OCDMA) PON uplink at 625 Mb/s [9,10]. In each case, the BM-CDRs have shown to achieve a BER < 10 −10 and a packet loss ratio (PLR) < 10 −6 while featuring instantaneous (0 preamble bit) phase acquisition for any phase step (±2π rad) between successive bursts.…”
Section: Burst-mode Receiversmentioning
confidence: 99%
“…high power consumption and poor jitter rejection characteristics [5]. Alternatively, time domain oversampling CDRs have demonstrated a CDR locking time of 8 ns [6]. However, they have high circuit complexity and high power consumption because they require a high frequency clock to drive the data sampler [5].…”
Section: Introductionmentioning
confidence: 99%
“…However, current work on clock phase caching have been purely experimental, and although analytical models of other approaches to CDR exist, such as for oversampling CDRs [6], [10], bang-bang phase interpolator CDRs [11] and for GVCO CDRs [10], no equivalent has been explored for the clock phase cached approach to CDR. Here, we introduce an analytical model of the bit error rate (BER) and CDR locking time performance of clock phase cached links.…”
Section: Introductionmentioning
confidence: 99%