5.9 Haswell: A family of IA 22nm processors

Kurd, Nasser; Chowdhury, Muntaquim; Burton, Edward A.; Thomas, Thomas P.; Mozak, Christopher; Boswell, Brent; Lal, Manoj B.; Deval, Anant; Douglas, Jonathan; Elassal, M.; Nalamalpu, Ankireddy; Wilson, Timothy M.; Merten, Matthew C.; Chennupaty, Srinivas; Gomes, Wilfred; Kumar, Rajesh

doi:10.1109/isscc.2014.6757361

Cited by 77 publications

(29 citation statements)

References 3 publications

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“…This rate is based on the performance of the integrated voltage regulator presented recently, which is implemented in the Intel Haswell [11]. According to Intel, the transition of the supply voltage from 0.8V to 1.05V for the turbo boost takes 100ns.…”

Section: Dvfs Assumptionsmentioning

confidence: 99%

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

Ando

Shioya

2016

IEICE Trans. Inf. & Syst.

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Hideki ANDO†a) and Ryota SHIOYA †b) , Members SUMMARY Dynamic instruction window resizing (DIWR) is a scheme that effectively exploits both memory-level parallelism and instruction-level parallelism by configuring the instruction window size appropriately for exploiting each parallelism. Although a previous study has shown that the DIWR processor achieves a significant speedup, power consumption has not been explored. The power consumption is increased in DIWR because the instruction window resources are enlarged in memoryintensive phases. If the power consumption exceeds the power budget determined by certain requirements, the DIWR processor must save power and thus, the performance previously presented cannot be achieved. In this paper, we explore to what extent the DIWR processor can achieve improved performance for a given power budget, assuming that dynamic voltage and frequency scaling (DVFS) is introduced as a power saving technique. Evaluation results using the SPEC2006 benchmark programs show that the DIWR processor, even with a constrained power budget, achieves a speedup over the conventional processor over a wide range of given power budgets. At the most important power budget point, i.e., when the power a conventional processor consumes without any power constraint is supplied, DIWR achieves a 16% speedup.

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Section: Dvfs Assumptionsmentioning

confidence: 99%

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

Ando

Shioya

2016

IEICE Trans. Inf. & Syst.

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“…To cater to these needs, modern processors are using large-sized memory structures, e.g., last level cache, main memory and storage. For example, Intel's 22 nm Haswell processor employs 128 MB eDRAM LLC (last level cache) [1], and the 22-nm Xeon E5-2600 processor has 45 MB SRAM LLC [2]. To address these challenges, researchers are exploring novel memory technologies, fabrication schemes and higher-density cell-designs.…”

Section: Introductionmentioning

confidence: 99%

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

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Abstract:To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2.

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“…Hardware manufacturers are increasingly prioritising energy efficiency in their processor designs [15]. Research suggests that software modifications will be required to fully exploit the resulting improvements in modern architectures [21].…”

Section: Introductionmentioning

confidence: 99%

Metrics for Energy-Aware Software Optimisation

Roberts

Wright

Fahmy

et al. 2017

Lecture Notes in Computer Science

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A note on versions:The version presented here may differ from the published version or, version of record, if you wish to cite this item you are advised to consult the publisher's version. Please see the 'permanent WRAP url' above for details on accessing the published version and note that access may require a subscription.For more information, please contact the WRAP Team at: wrap@warwick.ac.uk Metrics for Energy-Aware Software OptimisationStephen I. Roberts, Steven A. Wright, Suhaib A. Fahmy, and Stephen A. Jarvis University of Warwick, U.K. S.I.Roberts@warwick.ac.uk Abstract. Energy consumption is rapidly becoming a limiting factor in scientific computing. As a result, hardware manufacturers increasingly prioritise energy efficiency in their processor designs. Performance engineers are also beginning to explore software optimisation and hardware/software co-design as a means to reduce energy consumption. Energy efficiency metrics developed by the hardware community are often re-purposed to guide these software optimisation efforts. In this paper we argue that established metrics, and in particular those in the Energy Delay Product (Et n ) family, are unsuitable for energy-aware software optimisation. A good metric should provide meaningful values for a single experiment, allow fair comparison between experiments, and drive optimisation in a sensible direction. We show that Et n metrics are unable to fulfil these basic requirements and present suitable alternatives for guiding energy-aware software optimisation. We finish with a practical demonstration of the utility of our proposed metrics.

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5.9 Haswell: A family of IA 22nm processors

Cited by 77 publications

References 3 publications

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Metrics for Energy-Aware Software Optimisation

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