58.2: <i>Distinguished Paper</i>: Implementation of 240Hz 55‐inch Ultra Definition LCD Driven by a‐IGZO Semiconductor TFT with Copper Signal Lines

Gong, Namyong; Park, Chonghun; Lee, Jun-Ho; Jeong, Ilgi; Han, Hwadong; Hwang, Jeong-Tae; Park, Joon-Min; Park, Kwon‐Shik; Jeong, Hyemin; Ha, Yong‐Min; Hwang, Yong‐Kee

doi:10.1002/j.2168-0159.2012.tb05902.x

Cited by 39 publications

(25 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Compared to other competing TFT technologies, such as OTFT [3] and a-Si:H [4], a-GIZO TFTs show superior electrical mobility [5] and reliability [6]. Even though it was mainly meant for backplanes of AMOLED [7] and ultra definition LCDs [8], it is also finding extensive applications in driving circuits for back-planes of displays [9], [10] and RFIDs [11]. However, a-GIZO TFTs imposes various challenges in circuit design.…”

Section: Introductionmentioning

confidence: 99%

Analog Circuits With High-Gain Topologies Using a-GIZO TFTs on Glass

Bahubalindruni

Silva

Tavares

et al. 2015

J. Display Technol.

View full text Add to dashboard Cite

This paper presents analog building blocks that find potential applications in display panels. A buffer (source-follower), subtractor, adder, and high-gain amplifier, employing only n-type enhancement amorphous gallium-indium-zinc-oxide thin-film transistors (a-GIZO TFTs), were designed, simulated, fabricated, and characterized. Circuit simulations were carried out using a neural model developed in-house from the measured characteristics of the transistors. The adder-subtractor circuit presents a power consumption of 0.26 mW, and the amplifier presents a gain of 34 dB and a power consumption of 0.576 mW, with a load of 10 M pF. To the authors' knowledge, this is the highest gain reported so far for a single-stage amplifier with a-GIZO TFT technology.

show abstract

Section: Introductionmentioning

confidence: 99%

Analog Circuits With High-Gain Topologies Using a-GIZO TFTs on Glass

Bahubalindruni

Silva

Tavares

et al. 2015

J. Display Technol.

View full text Add to dashboard Cite

show abstract

“…As the size and resolution of the LCD increase, the resistance and capacitance (RC) loads of the display panel also increase, thus making it difficult to charge the subpixel and degrading the image quality of the display. Several thin‐film transistors (TFTs) have been researched for subpixel charging in the display panel, which is highly dependent on the characteristics of the TFTs used in the panel . Amorphous silicon TFTs and low‐temperature polysilicon TFTs have been widely used to date but have suffered from low mobility and non‐uniform characteristics, respectively .…”

Section: Introductionmentioning

confidence: 99%

“…Amorphous silicon TFTs and low‐temperature polysilicon TFTs have been widely used to date but have suffered from low mobility and non‐uniform characteristics, respectively . In recent years, indium gallium zinc oxide TFTs with relatively high mobility and uniform characteristics were developed for the backplane of displays in order to solve the subpixel charging issues in large‐sized and high‐resolution LCDs …”

Section: Introductionmentioning

confidence: 99%

“…Several thin-film transistors (TFTs) have been researched for subpixel charging in the display panel, which is highly dependent on the characteristics of the TFTs used in the panel. [1][2][3][4][5][6][7][8][9] Amorphous silicon TFTs and low-temperature polysilicon TFTs have been widely used to date but have suffered from low mobility and non-uniform characteristics, respectively. [1][2][3][4][5] In recent years, indium gallium zinc oxide TFTs with relatively high mobility and uniform characteristics were developed for the backplane of displays 6 in order to solve the subpixel charging issues in large-sized and high-resolution LCDs.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An optimal design method for minimization of common voltage distortion in large‐sized and high‐resolution liquid crystal displays

Kim

Kwon

2018

J Soc Info Display

View full text Add to dashboard Cite

This paper proposes an optimal design method that minimizes the common voltage (VCOM) distortion for large‐sized and high‐resolution liquid crystal displays (LCDs). Three design methods are examined using different architectures of the panel and circuit to compensate for the VCOM distortion. The proposed design method adopts a panel architecture that compensates for the VCOM distortion simultaneously at the top and bottom of the panel using a dual compensation circuit. It is implemented using a 27‐in. quad high‐definition LCD, and its VCOM distortion is further minimized by optimizing the compensation ratio of the dual compensation circuit. In addition, the minimized VCOM distortion is evaluated by measuring the horizontal crosstalk of the implemented panel according to the decrease in the charging time of the subpixel. As the charging time decreases from 11.6 to 7.8 μs, the measured crosstalk level varies from 0.10% to 1.06%, respectively, meeting the goal of less than 2%. Therefore, the proposed design method is suitable for large‐sized and high‐resolution LCDs requiring low VCOM distortion.

show abstract

“…Digital Object Identifier xxxxx evolving from niche to core technology in the flat panel display industry [1,2]. The stability of oxide TFTs has been studied by numerous research groups under negative gate bias stress that is important for AMLCDs, and positive gate bias stress to simulate driving transistors in AMOLED backplanes.…”

mentioning

confidence: 99%

A Study on the Degradation of In-Ga–Zn-O Thin-Film Transistors Under Current Stress by Local Variations in Density of States and Trapped Charge Distribution

Kim

et al. 2015

IEEE Electron Device Lett.

View full text Add to dashboard Cite

Thin film transistors using In-Ga-Zn-O (IGZO) semiconductors were evaluated under current stress by applying positive voltages to the gate and drain electrodes. Initially, the transfer characteristics exhibit identical threshold voltages (V T ) when the source and drain electrodes are interchanged during measurement ( forward and reverse V DS sweep). However as stress time increases, larger shifts in V T are observed under forward V DS sweep than under reverse V DS sweep conditions. Sub-gap states analyses based on the photoresponse of capacitance-voltage (C-V) curves suggest that local annihilation of donor-like traps occurs near the drain electrode. Hump-like features are clearly observed in the C-V curves collected between the drain and gate electrodes,while they do not appear in the C-V data obtained between the source and the gate. Based on the above, a local charge trapping model is introduced in order to interpret the device degradation. In this model, the major carrier electrons are trapped more abundantly near the source electrode due to the presence of a Schottky junction between IGZO and the source/drain electrodes.

show abstract

58.2: Distinguished Paper: Implementation of 240Hz 55‐inch Ultra Definition LCD Driven by a‐IGZO Semiconductor TFT with Copper Signal Lines

Cited by 39 publications

References 4 publications

Analog Circuits With High-Gain Topologies Using a-GIZO TFTs on Glass

Analog Circuits With High-Gain Topologies Using a-GIZO TFTs on Glass

An optimal design method for minimization of common voltage distortion in large‐sized and high‐resolution liquid crystal displays

A Study on the Degradation of In-Ga–Zn-O Thin-Film Transistors Under Current Stress by Local Variations in Density of States and Trapped Charge Distribution

Contact Info

Product

Resources

About