6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET

Im, Jungho; Dave, Freitas; Roldan, Arianne; Casey, Ronan; Chen, Stanley; Chou, Adam; Cronin, Tim; Geary, Kevin; McLeod, Scott; Zhou, Lei; Ian, Zhuang; Han, Jaeduk; Lin, Sen; Upadhyaya, Parag; Geoff, Zhang; Frans, Yohan; Chang, Ken

doi:10.1109/isscc.2017.7870287

Cited by 31 publications

(1 citation statement)

References 6 publications

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“…Fig. 2 shows half-rate DFE with speculative C1 tap, in which the upper DFE (above the dotted line) deals with odd data and lower DFE (below the dotted line) deals with even data [24,25]. Firstly, the adding and subtracting of tap coefficient C1 is performed in advance, and then the output signal of MUX is selected by the previous output.…”

Section: Half-rate Dfe With Speculative Tapmentioning

confidence: 99%

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

Zhang

Yang

2020

IEICE Electron. Express

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This paper presents a 36 Gb/s receiver equalizer including an adaptive continuous time linear equalizer (CTLE), which is based on slope detection and a half-rate speculative decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE with middle frequency compensation can not only adjust the ratio of high frequency and low frequency components adaptively, but also provide a small amount of equalization to middle frequency range. A half-rate speculative DFE, which is connected to the back of the CTLE, can satisfy the time constraints and eliminate the residual intersymbol interference. The chip area including pads is about 1.2 mm 2 and the power consumption is about 750 mW under 3.3 V power supply. Measurement results show that the receiver chip can effectively equalize 24 dB loss at Nyquist frequency and a clear eye diagram can be captured at 36 Gb/s.

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Section: Half-rate Dfe With Speculative Tapmentioning

confidence: 99%