A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

Aiming at the jitter issue in four-level pulse amplitude modulation (PAM4) receive link, the key causes related to the non-ideal effects of channel and data decision were analyzed, and a modified PAM4 receiver architecture was proposed. An analog equalizer with extra mid-frequency compensation and 1-tap decision-feedback equalizer were incorporated to minimize the inter-symbol interference. To alleviate the timing constraints in DFE, the feedback loop of slicer was optimized. The post-simulation results based on TSMC 28 nm CMOS process indicate that the proposed 50 Gb/s PAM4 receiver functions well over a channel with 12 dB loss at Nyquist frequency. The peak-to-peak jitters of two restored NRZ signals are 1.5 ps and 2.5 ps, respectively.

“…To overcome this issue, the MF compensation circuit shown in the right part of Fig. 4, which is different to the approach described in [28] is added. The result is displayed in Fig.…”

Section: Ctlementioning

confidence: 99%

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

Lv,

Xie,

Qin

et al. 2024

“…Common equalization techniques in high-speed serial links can be divided into liner equalizers (LE) and decision feedback equalizer (DFE) [5,6,7,8,9]. LE uses the frequency characteristics of the adjustable filter to compensate the channel loss, but for high-speed (> 5 Gbps) serial link, since the signal jitter (such as ISI related deterministic jitter) may exceed a symbol interval (UI), using LE alone is no longer applicable [10,11,12,13].…”

Section: Introductionmentioning

confidence: 99%

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

Zhu

Chu

2023

This work proposes a RX front-end structure, which is used for channel equalization of 25 Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19 dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005 mm 2 designed in 65 nm CMOS, the power consumption of which is 96 mW under 1.2 V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35 dB at 12.5 GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171 mV and 0.61 UI at the BER of 10 −12 , respectively.

“…The summer is the key module that affects the performance and power consumption of loop-unrolled half-rate DFE. Due to the existence of RC time constant formed by load resistance and parasitic capacitance, the resistively loaded CML summer has high DC power dissipation [20]. The switched-capacitor summer requires no DC power, but it needs more clock signals [21,22].…”

Section: Introductionmentioning

confidence: 99%

6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS

Sun

Zhang

Yang

2022

This paper presents a wide rate range receiver including adaptive continuous time linear equalizer (CTLE) and loop-unrolled half rate decision feedback equalizer (DFE). A hybrid filter is adopted to expand the rate range of adaptive CTLE with spectrum balancing technology. The current-integrating summer is introduced to reduce the power of half-rate loop-unrolled DFE. The post-simulation is carried out by 0.18 μm CMOS TSMC technology and the results show that the rate range of adaptive CTLE can reach to 6.25-10 Gb/s. When the 10 Gb/s PRBS7 signal is transmitted through the 18-inch FR4 backplane with 15.451 dB loss at Nyquist frequency, the eye diagram is obviously open and its horizontal opening is about 0.9 UI.