6.3: A Low‐EMI 2Gbps ClockAlignedtoData IntraPanel Interface (CADI) for TFT‐LCD with the VSYNC‐Embedded Clock and Equalization

Chi, Hyung-Joon; Choi, Young‐Ho; Lee, Soo-Min; Sim, Jae‐Yoon; Park, Hong-June; Lim, Jongjin; Kang, Pil-Sung; Lee, Bu-Yeol; Hong, Jin-Cheol; Lee, Hee-Sub

doi:10.1889/1.3500549

Cited by 2 publications

(2 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Another approach of the highspeed point-to-point signaling is to maintain both the clock and data lines for communication. The clock lines are arranged in the form of a point-to-point cascade [5] or a multi-drop [6] configuration. But to achieve higher bandwidth, a deskewing block composed of several analog circuits is implemented in a SD for compensating the arrival time difference between clock and data.…”

Section: Introductionmentioning

confidence: 99%

40.3: A 2Gbps/lane Source Synchronous Intra‐Panel Interface for Large Size and High Refresh Rate Panel with Automatic Calibration

Ozawa¹,

Akita²,

Suzuki³

et al. 2011

Symp Digest of Tech Papers

View full text Add to dashboard Cite

show abstract

Section: Introductionmentioning

confidence: 99%

40.3: A 2Gbps/lane Source Synchronous Intra‐Panel Interface for Large Size and High Refresh Rate Panel with Automatic Calibration

Ozawa¹,

Akita²,

Suzuki³

et al. 2011

Symp Digest of Tech Papers

View full text Add to dashboard Cite

show abstract

“…The relatively low frequency of clock signal helps to reduce electromagnetic interference (EMI). The scheme proposed in this brief is called the clock-aligned-to-data intrapanel (CADI) interface because an internal clock signal is generated so that its edge is aligned to the subpixel boundary of the incoming data signal at the RX [7].…”

Section: Introductionmentioning

confidence: 99%

A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL

Chi

Choi

Lee

et al. 2011

IEEE Trans. Circuits Syst. II

Self Cite

View full text Add to dashboard Cite

A 2-Gb/s point-to-point intrapanel interface for thinfilm-transistor liquid crystal display (TFT-LCD) is proposed by using only clock and data lines. Extra control lines are eliminated by sending the VSYNC code through the clock line at the start of the VBLANK time period and by sending the control commands through the data line at the end of the VBLANK time period. To reduce electromagnetic interference, the slew rate of the clock driver is reduced, and the frequency of clock signals is set to the subpixel (R/G/B) frequency (1/10 of the data rate). The clock line is cascaded between two adjacent receiver (RX) chips for a point-to-point interface. To generate an internal clock synchronized (deskewed) to the subpixel (R/G/B) boundary of incoming data at each RX, a single all-digital delay-locked loop (DLL) circuit is proposed to perform the combined operation of a DLL and a phase interpolator. This deskew operation is performed during the VBLANK period with periodic preamble data input ('1111100000'). At the RX, a multiphase DLL follows the deskewDLL to generate 20-phase clocks for data sampling. 2-Gb/s data are transmitted through a series connection of a 100-cm-long flat flexible cable and a 50-cm-long FR4 microstrip line with a bit error rate less than 1e-12. The image test was successfully performed with a 42-in full-high definition 120-Hz LCD panel at 1.5 Gbps. The area and power consumption of RX chip is 0.35 mm 2 and 52.4 mW at 2 Gbps with a 0.18-µm complementary metal-oxidesemiconductor process and a 1.8-V supply. Index Terms-Clock-Aligned-to-Data Intrapanel (CADI), deskew, DLL, intrapanel interface, point-to-point, thin-filmtransistor LCD, VSYNC.

show abstract

6.3: A Low‐EMI 2Gbps ClockAlignedtoData IntraPanel Interface (CADI) for TFT‐LCD with the VSYNC‐Embedded Clock and Equalization

Abstract: A point-to-point intra-panel interface for data and clock of TFT-LCD in 0.18um works at 2Gbps, with the 10~20dB EMI enhancement over the clock embedding scheme. The sub-pixel clock is cascaded with the transition time maximized for low EMI.

Cited by 2 publications

References 7 publications

40.3: A 2Gbps/lane Source Synchronous Intra‐Panel Interface for Large Size and High Refresh Rate Panel with Automatic Calibration

40.3: A 2Gbps/lane Source Synchronous Intra‐Panel Interface for Large Size and High Refresh Rate Panel with Automatic Calibration

A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL

Contact Info

Product

Resources

About