6.5 A 400Gb/s Transceiver for PAM-4 Optical Direct-Detect Application in 16nm FinFET

Loi, C.; Mellati, A.; Tan, A.; Farhoodfar, A.; Tiruvur, Arun; Helal, Belal M.; Killips, B.; Rad, F.; Riani, J.; Pernillo, Jorge; Sun, Ju; Wong, J.M.C.; Abdelhalim, Karim; Gopalakrishnan, Karthik; Kim, K.; Tse, L.; Davoodi, Majid; Le, M.Q.; Zhang, M.; Talegaonkar, Mrunmay; Prabha, Praveen; Mohanavelu, R.; Chong, Soogine; Forey, Simon; Netto, Sérgio L.; Bhoja, Sudeep; Liew, Wen-Sin; Duan, Yitao; Liao, Ying-Yu

doi:10.1109/isscc.2019.8662482

Cited by 25 publications

(15 citation statements)

References 5 publications

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“…Since its official release, PCIe (PCI-Express) has evolved rapidly and has become an indispensable technology for high-performance computer (HPC) communications [1], ethernet, industrial control, etc. The release of the PCIe 6.0 specification has dramatically increased computing speeds for applications such as HPC, cloud computing, and data center solid state drives (SSD), but with that comes the negative impact of the channel on clock signals and transmitted data.…”

Section: Introductionmentioning

confidence: 99%

A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0

et al. 2023

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As the PCIe 6.0 specification places higher requirements on signal integrity and transmission latency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface. Retimer circuits are a key component of high-speed serial interfaces, and their delay and jitter size directly affect the overall performance of PCIe. For the typical retimer circuit with large-latency and low-jitter performance, this paper proposes a low-latency and low-jitter Retimer circuit based on CDR + PLL architecture for PCIe 6.0, using a jitter-canceling filter circuit to eliminate the frequency difference between the retiming clock and data, reduce the retiming clock jitter, and improve the quality of Retimer output data. The data are sampled using the retiming clock and then output, avoiding the problem of large penetration latency of typical retimer circuits. The circuit is designed using the CMOS 28 nm process. Simulation results show that when 112 Gbps PAM4 data are input to the retimer circuit, the Retimer penetration latency is 27.3 ps, which is 83.5% lower than the typical Retimer structure; the output jitter data are 741 fs, a 31.4% reduction compared to the typical retimer structure.

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Section: Introductionmentioning

confidence: 99%

A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0

et al. 2023

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“…During the last years, there has been an increasing interest in the research of high-speed analog-to-digital converters (ADCs). This has been driven by the recent development in radar, electronic measurement, and especially high-speed transceiver for wireline communications [1][2] [3] [4].…”

Section: Introductionmentioning

confidence: 99%

“…To achieve tens of / sampling rates with resolution of around 7b, hierarchical time-interleaved ADCs have been widely used [3] [4]. A typical architecture block diagram of an 8x8 ways interleaved ADC is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC

Pasquo

Nani

Monaco

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a Track and Hold sampling buffer topology, which allows sampling the signal inside the buffer itself while achieving very high linearity. The circuit operations and its large-signal behavior are analyzed and the key design strategies to maximize linearity are discussed. Then, a / , . SFDR, 8 ways interleaved simulated prototype in TSMC technology, consuming . from a . supply, is compared to the state-ofthe-art sampling buffers, showing linearity improvement.

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“…In high-speed wireline communication links, limited channel bandwidth requires equalization in the transmitter (TX) and receiver (RX) to compensate for frequency-dependent loss [1]. Typically, the RX would employ adaptation algorithms to optimize their highly programmable equalizers to minimize bit error rate (BER) and power during operation [2], [3].…”

Section: Introductionmentioning

confidence: 99%

Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation

Zhang

Liang

Shahramian

et al. 2020

IEEE Solid-State Circuits Lett.

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A secondary communication link, or side-channel, is proposed, which uses binary frequency shift keying to modulate the frequency of a high-speed wireline transmitter clock. This side-channel data is then received using the corresponding receiver's conventional clock and data recovery (CDR) circuit. An analysis of the CDR loop parameters demonstrates that, within certain limits, the side-channel does not impact the signal integrity of the primary high-speed data. Measurements were made on a side-channel prototype using a 56-Gb/s PAM-4 (half-rate 14-GHz clock) transceiver in 7-nm FinFET technology through a 15-dB loss channel. Over 10 4 side-channel bits were transmitted at 50 kb/s, and the side-channel remained error-free with no visible impact on the high-speed link.

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6.5 A 400Gb/s Transceiver for PAM-4 Optical Direct-Detect Application in 16nm FinFET

Cited by 25 publications

References 5 publications

A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0

A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0

A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC

Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation

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