6.5L: <i>LateNews Paper</i>: The Enhanced Reduced Voltage Differential Signaling eRVDS Interface with Clock Embedded Scheme for ChipOnGlass TFTLCD Applications

Baek

et al. 2012

J Soc Info Display

Self Cite

-An intra-panel interface addressing all of the high-speed, low-power, and lowelectromagnetic interference (EMI) requirements for tablet personal computer applications is presented. This work proposes an adaptive clock window scheme to achieve 1.4-Gbps data-rate. For EMI suppression, data scrambling, horizontal blank period pattern scrambling, and novel clock and data recovery circuit are introduced. Lastly, for power-saving, the proposed interface dynamically biases source driver's output buffers and employs early charge sharing by controlling the configuration data. For verification, a WQXGA thin-film transistor liquid crystal display system is implemented with the timing controller and source driver ICs that are fabricated using 65-nm and 180-nm complementary metal-oxide semiconductor (CMOS) processes, respectively. The liquid crystal display system demonstrates maximum operation speed of 1.4 Gbps and suppression of EMI noise in LTE Band-20 and GSM 850 bands. The proposed power-saving schemes achieve 4.3% reduction in total power consumption by source driver IC, which reaches about 85% of power consumption by enhanced reduced-voltage differential signaling interface circuit.

Section: High‐speed Techniquementioning

confidence: 99%

A 1.4‐Gbps intra‐panel interface with low‐power and low‐EMI schemes for Tablet PC applications

Baek

et al. 2012

J Soc Info Display

Self Cite

“…For example, the intra‐panel interface that has 8 lanes over 1.2 Gbps is required to realize a WQXGA (2560 × 1600) resolution, 8 bit color depth, and 60‐Hz refresh rate. Many intra‐panel interfaces for the chip‐on‐glass (COG) application have been proposed to alleviate the speed limitations in COG technology . However, the interface between a stand‐alone TCON and driver ICs still accounts for a significant amount of power draw and increases manufacturing cost by using a flexible printed circuit, a printed circuit board, and passive elements related to the stand‐alone TCON.…”

Section: Introductionmentioning

confidence: 99%

A timing controller embedded driver IC with 3.24‐Gbps eDP interface for chip‐on‐glass TFT‐LCD applications

et al. 2016

This paper presents a timing controller embedded driver (TED) IC with 3.24‐Gbps embedded display port (eDP), which is implemented using a 45‐nm high‐voltage CMOS process for the chip‐on‐glass (COG) TFT‐LCD applications. The proposed TED‐IC employs the input offset calibration scheme, the zero‐adjustable equalizer, and the phase locked loop‐based bang‐bang clock and data recovery to enhance the maximum data rate. Also, the proposed TED‐IC provides efficient power management by supporting advanced link power management feature of eDP standard v1.4. Additionally, the smart charge sharing is proposed to reduce the dynamic power consumption of output buffers. Measured result demonstrates the maximum data rate of 3.24 Gbps from a 1.1 V supply voltage with a 7.9‐inch QXGA 60‐Hz COG‐LCD prototype panel and 44% power saving from the display system.

“…However the COG technology makes it difficult to operate at high data rate due to the limited bandwidth of channel on glass. An enhanced reduced voltage differential signaling (eRVDS) interface (shown in Figure 1) with clock embedded scheme has been proposed to alleviate the speed limitation in COG technology [1].…”

Section: Introductionmentioning

confidence: 99%

42.1: Distinquished Paper: A 1.4‐Gbps Intra‐Panel Interface for Chip‐On‐Glass TFT‐LCD Applications

Baek

Symp Digest of Tech Papers

et al. 2012

Self Cite

A high-speed intra-panel interface with an enhanced reduced voltage differential signaling (eRVDS) scheme is implemented in a 0.18-μm high-voltage CMOS process for the chip-on-glass (COG) TFT-LCD applications. The proposed interface employs the zero-adjustable equalizer to enhance the maximum data rate, the early charge sharing scheme to improve the interface data transfer efficiency, and dynamic biasing technique to reduce a power consumption of the output buffers. Measured result demonstrates the maximum data rate of 1.4 Gbps from a 1.8-V supply voltage with a WQXGA 60-Hz COG TFT-LCD prototype panel.