63 ps ECL circuits using advanced SICOS technology

Nakamura, Tohru; Ikeda, K.; Nakazato, Kazuhiko; Washio, Katsuyoshi; Namba, M.; Hayashida, Tomohiro

doi:10.1109/iedm.1986.191223

Cited by 11 publications

(1 citation statement)

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“…The hardware tkchnologies are: (1) Varied high-speed and high-density LSI chips using state-of-theart semiconductor technology -12K-gates 7Ops logical LSI chips and logic-and-memory LSI chips with ECL (Emitter Coupled Logic) technology suitable for a high speed processing LSI These LSI chips are fully used in the instruction processors and the system controllers of the M-880. (2) New micro carriers for LSI chip (MCCs) housing terminating resistors facilitating higher-density integration of large-scale LSI chips with high power dissipation and a large number of pins (3) High-density module consisting of a 44 layer mullite ceramic board, 106" by 106mm, capable of mounting up to 41 MCCs (4) Large-scale 46 layer low-dielectric-constant processor board, 730" by 534mm, capable of mounting up to 20 high-density modules by means of low insertion force connectors (2521 pins) (5) Direct water cooling mechanism to cool the highly-integrated components on the ceramic module boards efficiently Comb-shaped micro-fin cooling mechanism using special micro-fins and helium gas for high-density modules (6) Cabinet structure for a tightly coupled multiprocessor system, accommodating a low-voltage large-current compact DC power supply unit (DCUs), a power supply system, signal cables, and cooling pipes Figure 1 shows the configuration of the M-880 instruction processor.…”

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confidence: 99%

Hardware technology for Hitachi M-880 processor group

Kobayashi

Watanabe

Yamamoto

et al.

1991 Proceedings 41st Electronic Components &Amp; Technology Conference

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The HITACHI M-880 processor group, the newly developed top-of-the-line processors in HITACHI M Series computer family, feature ultrahigh performance, excellent reliability and eased installation requirements. To achieve their design goals, a new set of advanced hardware technologies have been developed in wide areas such as semiconductor, ceramic module board, printed circuit board, electric part, cooling and power feeding.

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mentioning

confidence: 99%

Hardware technology for Hitachi M-880 processor group

Kobayashi

Watanabe

Yamamoto

et al.

1991 Proceedings 41st Electronic Components &Amp; Technology Conference

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Merged bipolar transistor models including the substrate current

Inohira

Shinmi

Higuchi

et al. 1990

Electron Comm Jpn Pt II

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High integration density and high‐speed operation are obtainable by miniaturization of bipolar LSI devices. In modern bipolar integrated transistors, an undesired current flows into the substrate due to the parasitic sub‐PNP transistor. For example, for Bi‐CMOS circuits, this substrate current can be the main cause of reduction in the supply voltage. This paper proposes merged models for the NPN and lateral PNP transistors which include the substrate current due to the parasitic sub‐PNP transistor. The extraction of model parameters for the calculation of substrate current is also described. By the application of these models to the simulation of NPN transistor for Bi‐CMOS memory and lateral PNP transistor of linear process, good accuracy of dc saturation and substrate current characteristics can be obtained. Its application to the simulation of decoder/memory cell of Bi‐CMOS memory is demonstrated.

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High‐performance BIMOS using self‐aligning polysilicon electrode

Homma

Misawa

Momma

1990

Electron Comm Jpn Pt II

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To increase the speed of Hi‐BiCMOS, the process of forming an electrode which simultaneously reduces both parasitic capacitance and parasitic resistance in MOSFET's and bipolar transistors was investigated. Since the etching rate of highly doped polycrystalline silicon is higher than undoped polycrystalline silicon, arsenic‐doped polycrystalline silicon on the gate and emitter electrodes can be etched selectively. Self‐aligned polycrystalline silicon electrode technology (SPEL) using this phenomena was proposed. When the As concentration in polycrystalline Si is higher than 4 × 1020 cm−3, the doped polycrystalline Si is etched 10 times faster than undoped polycrystalline Si if plasma etching based on chlorine radicals is carried out. Using this process, the drain capacitance of the MOSFET was reduced one‐half to one‐third that of conventional devices. In bipolar transistors, collector resistance was reduced by a factor of 2 and the external base resistance was reduced by a factor of 3. As a result of simulating the performance of the device formed by the SPEL process, the gate delay time in a dual input NAND BiCMOS was 0.19 ns under no‐load condition while the gate delay time of the conventional device was 0.26 ns; that is, the speed of the SPEL device is 25 percent faster than that of the conventional device.

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63 ps ECL circuits using advanced SICOS technology

Cited by 11 publications

References 0 publications

Hardware technology for Hitachi M-880 processor group

Hardware technology for Hitachi M-880 processor group

Merged bipolar transistor models including the substrate current

High‐performance BIMOS using self‐aligning polysilicon electrode

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