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High integration density and high‐speed operation are obtainable by miniaturization of bipolar LSI devices. In modern bipolar integrated transistors, an undesired current flows into the substrate due to the parasitic sub‐PNP transistor. For example, for Bi‐CMOS circuits, this substrate current can be the main cause of reduction in the supply voltage. This paper proposes merged models for the NPN and lateral PNP transistors which include the substrate current due to the parasitic sub‐PNP transistor. The extraction of model parameters for the calculation of substrate current is also described. By the application of these models to the simulation of NPN transistor for Bi‐CMOS memory and lateral PNP transistor of linear process, good accuracy of dc saturation and substrate current characteristics can be obtained. Its application to the simulation of decoder/memory cell of Bi‐CMOS memory is demonstrated.

In modem integrated bipolar transistors with thin epitaxial layers, a parasitic current is often observed flowing into the substrate. This current causes the margin of the voltage sources in Bi-CMOS circuits [l] to decrease. In analog circuits, the saturation characteristics of the lateral PNP transistor is also influenced by the substrate current. This paper discusses merged bipolar transistor models which include the substrate current caused by the parasitic PNP transistor in the integrated device structure. Simple and accurate models for the NPN and lateral-PNP transistor are derived based on the integrated structure and physical considerations. Using these models, good accuracy of DC saturation and substrate current characteristics are obtained.One approach to introducing a substrate current into the circuit simulation is to use a combined model of an NPN and substrate PNP transistor [2]. However, this approach is not efficient because it needs a lot of nodes in the large circuit simulation. Since the substrate PNP transistor operates only as a parasitic current source, it is required to be as simple as possible. As the base-collector depletion layer of the substrate PNP transistor is formed in the side of p-type substrate, the Early effect on the PNP transistor can be neglected [3]. In addition, the parasitic transistor never operates in the saturation region. As a result, the substrate PNP transistor can be simplified as a diode (Is) and a current source (Isub). Figure l(a) shows a merged NPN transistor model derived from the considerations described above. In the merged modet, the substrate current Isub is represented by hub= l/qb Is b [ exp(V b'c'/V t) -11 (V t=kT/q) qb=1/2 ++/ U4 + Isb/Iks[exp(Vb'c'/Vt)-l] ,where qb is the normalized base charge similar to the Gummel-Poon model. The saturation current of the diode is given by Is=( l+qb/Ps) Isub .(3) ps, Isb and Iks represent the current gain, the saturation current and the knee current of the substrate PNP transistor, respectively. These three new parameters of the merged model can be determined from the Isub-Vbe characteristics. In using the model, it is important to extract the collector resistance Rc precisely by using the substrate current method[4], as shown in Table 1. It is also necessary to correct the value of the reverse currenit gain parameter PR, because a part of the base current flows through the diode (Is) into the substrate.In the case of the lateral PNP transistor, two parasitic substrate PNP transistors exist in the device structure. One exists under the p-type emitter layer and other under the p-type collector layer. From similar considerations to those of the NPN transistor, a merged model as shown in Fig. l(b) was obtained. In this model, the substrate current Isub is the sum of the current Isubl from the emitter side and the current Isub2 from the collector side. It is essential to correct the forward current gain parameter I~F.The merged models described above are introduced into a circuit simulator and applied to several bipolar d...

As analog ICs are finding use in a higher frequency band, a circuit simulator which is accurate in a high‐frequency region beyond 100 MHz becomes necessary. In this paper, a 600‐MHz wideband amplifier IC and its bipolar transistors and resistors are fabricated on an identical chip. By evaluating their S parameters, the accuracy of the device model was verified for simulation of analog IC at frequencies above 100 MHz. First, the parasitics of packages were modeled to verify the accuracy of the device model. It is shown that consideration of the resistance of pads is necessary. Next, the accuracy of the hybrid π model used widely as a high‐frequency model of the bipolar transistor was verified with the S parameters. It is found that the present form has poor accuracy at frequencies above 100 MHz. It is shown also that the IC structure of the transistor must be considered to improve the accuracy. Significant improvement of accuracy can be obtained if an extended model is introduced in which the separations of the base‐collector capacitance and the base‐emitter capacitance and the introduction of substrate resistance are included. Finally, by means of this extended model, a good high‐frequency simulation of a 600‐MHz wideband amplifier IC is realized.