In modem integrated bipolar transistors with thin epitaxial layers, a parasitic current is often observed flowing into the substrate. This current causes the margin of the voltage sources in Bi-CMOS circuits [l] to decrease. In analog circuits, the saturation characteristics of the lateral PNP transistor is also influenced by the substrate current. This paper discusses merged bipolar transistor models which include the substrate current caused by the parasitic PNP transistor in the integrated device structure. Simple and accurate models for the NPN and lateral-PNP transistor are derived based on the integrated structure and physical considerations. Using these models, good accuracy of DC saturation and substrate current characteristics are obtained.One approach to introducing a substrate current into the circuit simulation is to use a combined model of an NPN and substrate PNP transistor [2]. However, this approach is not efficient because it needs a lot of nodes in the large circuit simulation. Since the substrate PNP transistor operates only as a parasitic current source, it is required to be as simple as possible. As the base-collector depletion layer of the substrate PNP transistor is formed in the side of p-type substrate, the Early effect on the PNP transistor can be neglected [3]. In addition, the parasitic transistor never operates in the saturation region. As a result, the substrate PNP transistor can be simplified as a diode (Is) and a current source (Isub). Figure l(a) shows a merged NPN transistor model derived from the considerations described above. In the merged modet, the substrate current Isub is represented by hub= l/qb Is b [ exp(V b'c'/V t) -11 (V t=kT/q) qb=1/2 ++/ U4 + Isb/Iks[exp(Vb'c'/Vt)-l] ,where qb is the normalized base charge similar to the Gummel-Poon model. The saturation current of the diode is given by Is=( l+qb/Ps) Isub .(3) ps, Isb and Iks represent the current gain, the saturation current and the knee current of the substrate PNP transistor, respectively. These three new parameters of the merged model can be determined from the Isub-Vbe characteristics. In using the model, it is important to extract the collector resistance Rc precisely by using the substrate current method[4], as shown in Table 1. It is also necessary to correct the value of the reverse currenit gain parameter PR, because a part of the base current flows through the diode (Is) into the substrate.In the case of the lateral PNP transistor, two parasitic substrate PNP transistors exist in the device structure. One exists under the p-type emitter layer and other under the p-type collector layer. From similar considerations to those of the NPN transistor, a merged model as shown in Fig. l(b) was obtained. In this model, the substrate current Isub is the sum of the current Isubl from the emitter side and the current Isub2 from the collector side. It is essential to correct the forward current gain parameter I~F.The merged models described above are introduced into a circuit simulator and applied to several bipolar d...