64.5L: <i>Late‐News Paper</i>: A Clock Embedded Differential Signaling (CEDS™) for the Next Generation TFT‐LCD Applications

Jeon, Hye Kyung; Moon, Y. H.; Seo, Jeong-II; Na, Joon-Ho; Oh, Hyung-Seog; Han, Dae-Keun; Kang, Pil-Sung; Jeong, Yang-Seok; Park, Man-Gyu; Seung-Cheol, O; Hong, Jin-Cheol; Kim, Lee-Sup

doi:10.1889/1.3256962

Cited by 10 publications

(14 citation statements)

References 6 publications

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“…Mostly to make the data transition edges, in the PLL based CDR, use balance code such as 8B/10B or 4B/5B. This codes increase in protocol overhead of as much as 25% [13].For an example, in the CEDS protocol [14], the width of dummy bits is two UI. For the UI of 250ps, this width is not the bottleneck for phase alignment.…”

Section: Topology and Retiming Scheme Of Cdrmentioning

confidence: 99%

13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface

Zhengcai¹

2019

Symp Digest of Tech Papers

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This work presents a front‐end circuits including of the equalizer and clock/data recovery (CDR) circuits in the source driver ICs (SDICs) for the TFT‐LCD intra‐panel interfaces. For 4K2K LCD TV, the data rate of SDICs has been increased to 5Gbps per lane, so it is a challenge to develop the front‐end circuits when they suffered from the serious ISI and large jitters in received data. In the front‐end circuits meeting the BOE’s CHPI specification, a cascade equalizer are used to widen the eye diagram to reduce BER and a dual loop CDR circuits are used to tolerate the large input jitter and power noise.

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Section: Topology and Retiming Scheme Of Cdrmentioning

confidence: 99%

13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface

Zhengcai¹

2019

Symp Digest of Tech Papers

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“…Point-to-point topology in the intra-panel interface has smaller EMI and lower hardware cost compared to the multi-drop topology [1]. By utilizing the clock-embedded signaling (CES) scheme, the clock lane can be omitted, further reducing the hardware cost.…”

Section: Introductionmentioning

confidence: 99%

A dual-edge sampling CES delay-locked loop based clock and data recovery circuits

Goh

Lee

Chang

2015

VLSI Design, Automation and Test(VLSI-Dat)

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This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area of the test chip is 0.519*0.137 mm 2 and the power efficiency of the proposed CDR is 1.43 mW/Gb/s with wide operating range of 0.5 Gb/s to 3.0 Gb/s.

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“…However, the skew problems between the data and clock signals still restrict higher frequency operation and result in EMI issues. To further eliminate these problems, several clock embedded methods in the form of multi-level signaling [5], the time multiplexed [6] scheme, and Run-Length-Limited (RLL) encoding [7] were proposed. Nevertheless, there were some bottlenecks of these interfaces to be applied to COG applications because of the defective environment on the glass.…”

Section: Introductionmentioning

confidence: 99%

42.4: The Integrated‐Stream Protocol (iSP) Interface with Clock Embedded Scheme for the Next Generation TFT‐LCD Applications

Chang

Huang

Chung

et al. 2012

Symp Digest of Tech Papers

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This paper presents an integrated-Stream Protocol (iSP) interface that is capable of high data rate operation with less signal lines for the next generation TFT-LCD application. An 8b/9b encoding technique is employed to synchronize the system without separate clock and control signal lines, and it achieves low overhead and electromagnetic interference (EMI) performance. In order to compensate the channel attenuation, the receiver is equipped with the equalizer function. The power consumption is effectively reduced by applying the transfer-impedance amplifier (TIA) receiver. The iSP interface has been verified on an 11.6-inch full-HD Chip-On-Glass (COG) TFT-LCD panel with 1.35Gbps data rate. Additionally, it could be operated at higher data rate up to 1.8Gbps on Chip-On-Board (COB) platform.

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64.5L: Late‐News Paper: A Clock Embedded Differential Signaling (CEDS™) for the Next Generation TFT‐LCD Applications

Cited by 10 publications

References 6 publications

13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface

13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface

A dual-edge sampling CES delay-locked loop based clock and data recovery circuits

42.4: The Integrated‐Stream Protocol (iSP) Interface with Clock Embedded Scheme for the Next Generation TFT‐LCD Applications

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