This paper presents an integrated-Stream Protocol (iSP) interface that is capable of high data rate operation with less signal lines for the next generation TFT-LCD application. An 8b/9b encoding technique is employed to synchronize the system without separate clock and control signal lines, and it achieves low overhead and electromagnetic interference (EMI) performance. In order to compensate the channel attenuation, the receiver is equipped with the equalizer function. The power consumption is effectively reduced by applying the transfer-impedance amplifier (TIA) receiver. The iSP interface has been verified on an 11.6-inch full-HD Chip-On-Glass (COG) TFT-LCD panel with 1.35Gbps data rate. Additionally, it could be operated at higher data rate up to 1.8Gbps on Chip-On-Board (COB) platform.

This paper presents an intra-panel interface that adopts a skewless point-to-point mini-LVDS (SPPmL) using 240 Hz of driving technology. A differential data signal with an embedded code was applied between the timing controller (TCON) and column driver ICs (DICs) to synchronize the clock and data. The synchronization core circuit was based on a delay cell that eliminates clock and data skew problems. Power consumption was effectively reduced using a delay cell circuit lower than using a phase-locked loop (PLL) and a delay-locked loop (DLL) circuit. The proposed SPPmL interface was verified on a 65-in. full HD (1920×1080) TFT-LCD panel to achieve the high data transfer rate required for high-resolution LCD models. The measured results show that the maximum data rate is higher than 2.0 Gb/s.