P‐42: Skew‐less Point‐to‐Point Mini‐LVDS (SPPmL) Interface for Large‐Scale TFT‐LCD Applications

Abstract

This paper presents an intra-panel interface that adopts a skewless point-to-point mini-LVDS (SPPmL) using 240 Hz of driving technology. A differential data signal with an embedded code was applied between the timing controller (TCON) and column driver ICs (DICs) to synchronize the clock and data. The synchronization core circuit was based on a delay cell that eliminates clock and data skew problems. Power consumption was effectively reduced using a delay cell circuit lower than using a phase-locked loop (PLL) and a delay-locked loop (DLL) circuit. The proposed SPPmL interface was verified on a 65-in. full HD (1920×1080) TFT-LCD panel to achieve the high data transfer rate required for high-resolution LCD models. The measured results show that the maximum data rate is higher than 2.0 Gb/s.