64 bit monolithic floating point processors

Ware, F.; McAllister, William; Carlson, J.R.; Sun, Di-Shi; Vlach, Radek

doi:10.1109/jssc.1982.1051837

Cited by 23 publications

(3 citation statements)

References 6 publications

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“…It uses short wires that go from one full adder to adjacent full adders horizontally, vertically or diagonally. [4] In array multiplier, consider two binary numbers A and B, of m and n bits. There are mn summands that are produced in parallel by a set of mn AND gates.…”

Section: Array Multipliermentioning

confidence: 99%

Comparison Between Array Multiplier and Vedic Multiplier

2018

IJRTER

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One of the most important arithmetic unit in DSPs and microprocessors is multiplier. It is also a major source of power dissipation. To reduce the power dissipation of multipliers is the key to satisfy the overall budget of digital circuits. This paper analyses and compares array multiplier with vedic multiplier so that we can select a better multiplier design to perform multiplication of two numbers. The main objective of our work is to calculate and compare the total number of LUTs utilized by array and vedic multipliers. The designs are done using ISE Design Suit 14.4 tool and are simulated using Modelsim 10.0c (Student edition) simulator.

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Section: Array Multipliermentioning

confidence: 99%

Comparison Between Array Multiplier and Vedic Multiplier

2018

IJRTER

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“…3. It uses short wires that go from one full adder to adjacent full adders horizontally, vertically or diagonally [3] . …”

Section: Array Multiplicationmentioning

confidence: 99%

Design and implementation of 4-bit Vedic Multiplier

Maiti¹

2016

ijetst

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Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). This paper proposes the design of high speed Vedic Multiplier using the techniques of Vedic Mathematics that have been modified to improve performance .The need of high speed multiplier is increasing as the need of high speed processors are increasing . A Multiplier is one of the key hardware blocks in most fast processing system which is not only a high delay block but also a major source of power dissipation.A conventional processor requires substantially more hardware resources and processing time in the multiplication operation, rather than addition and subtraction.

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“…A comparison of the hardware requirements for shiftand-add parallel array multiplier and modified Booth parallel multiplier [5,6] is given in Table 11. Carry propagation is an important factor in the design of parallel multipliers.…”

Section: Table I Modified Booth Multiplication Schemementioning

confidence: 99%

Multiply-add fused RISC architectures for DSP applications

Panneerselvam

Nowrouzian

Proceedings of IEEE Pacific Rim Conference on Communications Computers and Signal Processing

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Absmct-This paper presents the development of a fixedpoint bit-parallel multiply-add f d (MAF) architecture together with a corresponding V U 1 implementation. The proposed MAF implementation employs the 1.w CMOS technology provided by the Northem Telecom Electronics and available through the Cnnadian Micmdectrpnics Corporation (CMC). This MAF implementation finds a variety of practical applications in high-speed real-time digital signal processing (DSP). The MAF implementation employs a parallel modified Booth multiplier incorporating M array of carry-save adders for the addition 01 the intermediate partial products, and a hardware eifldent carry-skip adder for carry propagation.

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64 bit monolithic floating point processors

Cited by 23 publications

References 6 publications

Comparison Between Array Multiplier and Vedic Multiplier

Comparison Between Array Multiplier and Vedic Multiplier

Design and implementation of 4-bit Vedic Multiplier

Multiply-add fused RISC architectures for DSP applications

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