64-bits low power CMOS SRAM by using 9T cell and charge recycling scheme

Singhal, Varun Kumar; Singh, Balwinder

doi:10.1109/icdcsyst.2012.6188781

Cited by 1 publication

(1 citation statement)

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“…In reported paper [2] authors have discussed sleep stack technique wherein multiple cell voltages have been used to reduce the leakage power. Careful selection of cell voltages reduces the leakage current up to a certain extent, also in [15] dynamic voltage scaling been discussed which says that during a fixed period of time the activity in a cache is only centered on a small subset of the lines. This behavior has been exploited to cut the leakage power of large caches by putting the cold cache lines into a state preserving low-power drowsy mode but Moving lines into and out of drowsy state incurs a slight performance loss [13].…”

Section: Sram Reviewmentioning

confidence: 99%

A Novel Switched Capacitor Technique for NBTI Tolerant Low Power 6T-SRAM Cell Design

Dongre¹,

Pattanaik²,

Raj³

et al. 2014

IOSRJVSP

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The work in this paper is focused on designing a NBTI tolerant 6T SRAM cell while maintaining low power operation. We explore the usefulness of switched capacitor circuit to provide NBTI tolerance while reducing overall power consumption. A thorough analysis of the 6T SRAM cell has been done to show the reduction in power consumption of the cell without degrading the read and write stability. The results obtained in proposed technique are compared and contrasted with reported data for the validation of our approach. The proposed technique reduces read power by 32%, write power by 15% and leakage power by 14%. The applied technique effectively reduces overall current by considerable amount and also significant reduction in Vth degradation due to NBTI is observed hence it is suitable for NBTI tolerant low power 6T SRAM cell design.

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Section: Sram Reviewmentioning

confidence: 99%