7.2 A 20.5TOPS and 217.3GOPS/mm<sup>2</sup> Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications

Yamada, Y.; Sano, Tsuyoshi; Tanabe, Yoshinori; Ishigaki, Yutaro; Hosoda, Soichiro; Hyuga, Fumihiko; Moriya, Akio; Hada, Ryuji; Masuda, Atsushi; Uchiyama, Masato; Koizumi, Toru; Tamai, Takanori; Sato, Nobuhiro; Tanabe, Jun; Kimura, Kozo; Murakami, Ryusuke; Yoshikawa, Takashi

doi:10.1109/isscc.2019.8662459

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Trends In Recent Cnn Accelerator1

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Cited by 6 publications

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“…In this section, we review recent trends in CNN accelerator research which are not covered in the previous sections. In the previous sections, we mentioned the trends of CNN accelerators, for example, large on-chip memories (144MB [51], 220MB [56]), 8bit fixed point MAC units and 16bit floating point MAC units for CNN accelerators, popularity of streaming architectures [41][52] [53].…”

Section: Trends In Recent Cnn Acceleratormentioning

confidence: 99%

A Survey on System-Level Design of Neural Network Accelerators

Seto

2021

JICS

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In this paper, we present a brief survey on the system-level optimizations used for convolutional neural network (CNN) inference accelerators. For the nested loop of convolutional (CONV) layers, we discuss the effects of loop optimizations such as loop interchange, tiling, unrolling and fusion on CNN accelerators. We also explain memory optimizations that are effective with the loop optimizations. In addition, we discuss streaming architectures and single computation engine architectures that are commonly used in CNN accelerators. Optimizations for CNN models are briefly explained, followed by the recent trends and future directions of the CNN accelerator design.

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Section: Trends In Recent Cnn Acceleratormentioning

confidence: 99%