70GHz CMOS Harmonic Injection-Locked Divider

Yamamoto, Ken; Fujishima, Minoru

doi:10.1109/isscc.2006.1696311

Cited by 83 publications

(53 citation statements)

References 4 publications

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“…TUNING MECHANISM OF RILFD Generally, ILFDs have been designed with two kinds of VCOs such as an LC-type [3][4][5][6][7][8][9] and a ring-type oscillator [10][11][12][13][14][15][16][17]. To inject an input signal to the oscillator, direct and tail injection methods are used.…”

Section: Operating Speed Improvement and Frequencymentioning

confidence: 99%

A 110GHz inductor-less CMOS frequency divider

Lim

Badalawa

Fujishima

2009

2009 IEEE Asian Solid-State Circuits Conference

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An inductor-less 110GHz ring-type frequency divider (RILFD) has been proposed. Body-injection and biasing technique have been adopted to achieve high speed and divideby-three operation and fine tuning of operation frequency. The RILFD was fabricated by a 1P12M 65nm bulk CMOS process. The core size is 10.8×8.5μm2. The locking range is 9.1%, from 100.8 to 110.4GHz, under varying of body-bias voltage from -0.2V to 0.4V. The RILFD consumes 4.5mW at the supply voltage of 1V excluding an output buffer. The output phase noise is -117.6dBc/Hz at 1MHz offset. This work has been achieved the smallest core size among frequency dividers reported to date operating over 100GHz.

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Section: Operating Speed Improvement and Frequencymentioning

confidence: 99%

A 110GHz inductor-less CMOS frequency divider

Lim

Badalawa

Fujishima

2009

2009 IEEE Asian Solid-State Circuits Conference

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“…To lower the power consumptions, the design of the singlestage divide-by-4 divider [3,4] has been carried out for a while however, and the locking range is narrow. In this letter we propose novel divide-by-4 ILFDs with active inductors.…”

Section: Introductionmentioning

confidence: 99%

“…Conventional radio-frequency (RF) transceivers often use injection-locked frequency dividers (ILFDs) in the feedback path of a phase-locked loop [1] to achieve frequency multiplication and in the RF front-end section as a part of frequency plan [2,3], so that an oscillating frequency source different from the master VCO can be generated. Because of their importance to the whole RF transceiver systems, recently the study of ILFDs has received a great attention.…”

Section: Introductionmentioning

confidence: 99%

Wide‐locking range divide‐by‐4 injection‐locked frequency dividers

Jang

Liu

2008

Micro & Optical Tech Letters

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“…These alternatives include the Miller regenerative topology and injection-locked oscillators, both of which suffer from a narrow lock range at very high frequencies. For example, the injection-locked divider in [1] achieves a lock range of about 1.5% if no external tuning is applied. Furthermore, these topologies do not readily lend themselves to divide ratios greater than 2 [2].…”

mentioning

confidence: 99%

“…Using a relatively high loop gain (while maintaining a reasonable phase margin), the PLL can achieve a lock range almost equal to the tuning range of the oscillator, which is typically 5 to 10 times the lock range of an injection-locked divider. Note that external (discrete or continuous) tuning techniques applied to injection-locked dividers [1,2] can be used here as well to further widen the lock range.…”

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confidence: 99%

Heterodyne Phase Locking: A Technique for High-Frequency Division

Razavi¹

2007

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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The task of frequency division entails serious challenges at speeds greater than a few tens of gigahertz as flip-flop-based topologies fail and narrowband alternatives emerge as the only viable solution. These alternatives include the Miller regenerative topology and injection-locked oscillators, both of which suffer from a narrow lock range at very high frequencies. For example, the injection-locked divider in [1] achieves a lock range of about 1.5% if no external tuning is applied. Furthermore, these topologies do not readily lend themselves to divide ratios greater than 2 [2]. This paper introduces the concept of "heterodyne phase locking," a technique that can be used to construct high-speed dividers with arbitrary integer or fractional divide ratios. Consider the phase-locked loop (PLL) shown in Fig. 23.6.1, where the phase detector (e.g., a single mixer) is replaced with a cascade of N mixers that are driven by the voltage-controlled oscillator (VCO) output. It is assumed that each mixer is followed by a filter to remove the sum frequency generated by that mixer. In a manner similar to a heterodyne receiver, this cascade of mixers downconverts the input N times, producing a dc component at node X if f in =N•f out . In other words, if the loop locks, then f out =f in /N.Heterodyne phase locking offers a number of advantages over other frequency division techniques. First, a divide ratio of, say, 3 is as easily afforded as a divide ratio of 2 -a sharp contrast to flip-flop-based and injection-locked topologies. In fact, as N increases, the only trade-offs that arise are from the necessary reduction of the loop bandwidth, which is tolerable so long as the settling of the PLL is much faster than that of the synthesizer in which it is embedded, and the higher loading imposed on the oscillator, which can be accommodated because the oscillator operates at a proportionally lower frequency.The second advantage is associated with the lock range. Using a relatively high loop gain (while maintaining a reasonable phase margin), the PLL can achieve a lock range almost equal to the tuning range of the oscillator, which is typically 5 to 10 times the lock range of an injection-locked divider. Note that external (discrete or continuous) tuning techniques applied to injection-locked dividers [1, 2] can be used here as well to further widen the lock range.The third advantage relates to the output phase noise. Injectionlocked dividers, if designed for higher speeds, require that, on the one hand, the tank Q be scaled up to maintain a constant phase noise and, on the other hand, the tank Q be constant to maintain a constant fractional lock range. Therefore, these dividers suffer from a trade-off between the tank Q and produce greater phase noise as the circuit approaches the edge of the lock range. Heterodyne PLLs, however, entail no such trade-offs if their loop gain remains high.Heterodyne phase-locking can also provide fractional divide ratios. If a ÷M circuit is inserted in the feedback path of Fig. 23.6.1, then f out =M•...

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70GHz CMOS Harmonic Injection-Locked Divider

Cited by 83 publications

References 4 publications

A 110GHz inductor-less CMOS frequency divider

A 110GHz inductor-less CMOS frequency divider

Wide‐locking range divide‐by‐4 injection‐locked frequency dividers

Heterodyne Phase Locking: A Technique for High-Frequency Division

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