8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range

Bowman, Keith; Raina, Sarthak; Bridges, Todd S.; Yingling, Daniel; Nguyen, Hoan; Appel, Brad; Kolla, Yesh; Jeong, Jihoon; Atallah, Francois; Hansquine, David

doi:10.1109/isscc.2015.7062971

Cited by 12 publications

(7 citation statements)

References 6 publications

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“…Error detection and recovery costs have decreased from 44 additional transistors per flip-flop for detection and dozens of clock cycles for recovery in the first Razor design [23], to only 3 additional transistors and as few as a single clock cycle in the latest version [65]. Likewise, recent advances in the design of ultra-fast on-chip voltage regulators and all-digital phase locked loops with subnanosecond response times have increased the potential benefits by enabling more aggressive timing speculation schemes [24][37] [8].…”

Section: Timing Speculationmentioning

confidence: 99%

Performance Analysis of Timing-Speculative Processors

Assare

Gupta

2022

IEEE Trans. Comput.

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Section: Timing Speculationmentioning

confidence: 99%

Performance Analysis of Timing-Speculative Processors

Assare

Gupta

2022

IEEE Trans. Comput.

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“…However, this GB costs significant additional power, since power increases as Vdd 2 and therefore also increases as GB 2 . To optimize the power consumption, there have been significant efforts to detect and mitigate these droops, to reduce the GB [2][3][4][5][6][7][8][9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

“…The digital droop detectors can be simpler to design, synthesizable, and could potentially provide a high-resolution signal across a wide voltage range. Once a droop is detected, several options have been suggested to mitigate it, including architectural instruction throttling [4], adaptive frequency throttling [7,10] and charge injection [3].…”

Section: Introductionmentioning

confidence: 99%

A 8800 μm² CCO-Based Voltage-Droop and Temperature Detector in 65 nm

2021

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The Vcc level and temperature of IC's are important parameters which determine the power / performance. Resonances in the package and platform can cause significant AC voltage droops which can degrade functionality, requiring additional guard-band. Prior-art droop detectors utilize digital delay circuits, such as tunable replica circuits to measure these droops. However, the delay is a strong function of temperature as well as the DC Vcc level, making it difficult to differentiate the AC droop across different voltage and temperature levels. It is proposed to utilize a current controlled oscillator (CCO) with an analog bias to mitigate the voltage and temperature dependencies, such that only the AC droop is measured. The CCO frequency is independent of the DC Vcc level, while the temperature is also characterized along with the AC droop, such that both temperature and droop levels can be extracted. The sensor can measure droops and temperature to an accuracy of 10mV and ±3 o C respectively. The circuit occupies 8800 μm 2 in 65nm with a power consumption of 297 µW. This circuit is very useful to characterize the power grid in design for test (DFT) applications as well as on-the-fly real time chip operation.

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“…In [9], an on-die high-frequency supply droop detector using analog circuit [59], an adaptive clocking scheme using a critical path replica is proposed to modulate the global system clock and local clocks in presence of power supply noise. The droop monitoring circuits in both [61] and [59] monitor supply variation above 0.7V and consume higher power as compared to the proposed droop measurement scheme in this paper.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…Noise due to package resonance and low-frequency droops takes time to recover and thus is present for multiple clock cycles and impacts performance globally across the chip. Existing work in literature such as [61] has proposed on-die dynamic voltage monitoring and adaptive clock distribution schemes to enable tolerance to power supply variations across a wide operating range. In [62], techniques for timing error detection and correction are proposed to reduce metastability occurring due to dynamic power supply and temperature variations.…”

Section: Introductionmentioning

confidence: 99%

Power Management in Ultra-Low Power Systems

Roy¹

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The evolving vision of the Internet-of-Things (IoT) will revolutionize various applications such as remote health monitoring, home automation and remote surveillance. It has been projected that by 2025, there will be 1 trillion IoT devices influencing our daily lives. This will result in the generation of an enormous amount of data, which will have to be stored, processed and transmitted efficiently and reliably. Although advancements in Integrated Circuit (IC) design and the availability of various Ultra-low Power (ULP) circuit components have helped us to visualize an ecosystem of numerous internet-connected devices, the overall system integration will become a major challenge. A System-on-Chip (SoC), catering to IoT applications is expected to contain many different circuit components such as sensors and Analog-Front-Ends (AFEs) for real-time signal acquisition, analog-to-digital converters, digital signal processors, memories, wireless transceivers etc. All these components have different supply voltage requirements and power profiles. Hence, power delivery to such components in an SoC will play an important role in the overall system architecture. Although, battery-powered systems have traditionally worked well in portable electronics but in an IoT ecosystem, the cost of battery replacement in a trillion-sensor node network will be enormous. In many applications, such as remote surveillance, systems require a long operational lifetime. Moreover, system deployment should be unobtrusive and hence such systems should have small form factors.The above requirements are hard to meet using conventional battery-powered systems. Hence, in most IoT SoCs, there is a strong motivation for an integrated Power Management Unit (PMU), with energy harvesting capability for near-perpetual battery-less operation, which i Abstract ii can provide a range of supply voltage rails to satisfy the electrical specifications of different functional units.This dissertation addresses the design challenges related to energy autonomy and powerdelivery in a wireless sensor node. This work presents an energy harvesting platform in context of a self-powered System-in-Package (SiP) with a capability to harvest from either photovoltaic or thermoelectric generators (TEGs). The SiP consists of an SoC for processing and storage, non-volatile memory, a wireless transceiver and various off-the-shelf sensors. To deliver power and to meet the electrical specifications of these different components of the sensor node, this work presents an efficient, low quiescent power, supply-voltage regulation scheme. In addition to power delivery, this dissertation also demonstrates several ULP digital and mixed-signal circuit components, commonly used in energy-autonomous and always-ON systems such as an event-driven wakeup receiver. This work describes circuit solutions and techniques related to power delivery that will enhance the operational lifetime, reduce the overall form-factor and contribute towards attaining energy-autonomy to facilitate a wide range of a...

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8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range

Cited by 12 publications

References 6 publications

Performance Analysis of Timing-Speculative Processors

Performance Analysis of Timing-Speculative Processors

A 8800 μm² CCO-Based Voltage-Droop and Temperature Detector in 65 nm

Power Management in Ultra-Low Power Systems

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