8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with &gt;40dB Channel Loss in 7nm FinFET

Mishra, Parmanand; Tan, A.; Helal, Belal M.; Ho, Ching-Huai; Loi, C.; Riani, J.; Sun, Ju; Mistry, K.; Raviprakash, K.; Tse, L.; Davoodi, Majid; Takefman, M.; Fan, Na; Prabha, Praveen; Liu, Q.; Wang, Q.; Nagulapalli, Rajasekhar; Cyrusian, S.; Jantzi, S.; Scouten, S.; Dusatko, Tomas A.; Setya, T.; Giridharan, V.; Gurumoorthy, Vivekananth; Karam, Vincent; Liew, Wen-Sin; Liao, Ying-Yu; Ou, Y-C.

doi:10.1109/isscc42613.2021.9365929

Cited by 53 publications

(11 citation statements)

References 4 publications

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“…where g m2 R D2 is the voltage gain of the cross-coupled CG stage. According to (7), the CG stage creates a zero that leads to a peaking in the frequency response of Z inÀdif f at the following frequency.…”

Section: Cross-coupled Regulated Cascode Structurementioning

confidence: 99%

“…3 To overcome these drawbacks, different inductorless techniques have been introduced to increase bandwidth in some literatures. [4][5][6][7] In Chien and Chan, 8 capacitive peaking approach is utilized, which provides an extra pole to implement a well-controlled Butterworth response and thus enhances the bandwidth. Also, Lu et al 9 employ capacitive degeneration technique to add an extra zero to compensate for the dominant pole created by C PD .…”

Section: Introductionmentioning

confidence: 99%

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A 12.5 Gb/s 0.13‐μm CMOS inductorless transimpedance amplifier with 1 pF input capacitance for optical communications

Parapari

Koozehkanani

et al. 2022

Circuit Theory & Apps

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Summary This paper proposes an inductorless fully differential transimpedance amplifier (TIA) with a single‐ended photo current to offer high bandwidth for applications of beyond 10 Gb/s optical communications. The presented TIA provides a much lower input impedance by modifying the cross‐coupled regulated cascode (CC‐RGC) configuration. The introduced method is able to enhance the bandwidth in the presence of wide range of input photodiode capacitance from small to large values, with a negligible increase in the peaking of frequency response. The proposed circuit is designed and simulated using the TSMC 130‐nm CMOS technology to validate the proposed technique. The post‐layout simulation results show that the TIA delivers a transimpedance gain of 46.5 dB normalΩ, a bandwidth of 8.8 GHz, and an input‐referred current noise of 33 pA/√Hz. The circuit occupies an active area of 0.004 mm2 and consumes 9.8 mW from a 1.3 V supply. Furthermore, the robustness of the proposed TIA is verified by means of the Monte Carlo simulations.

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Section: Cross-coupled Regulated Cascode Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 12.5 Gb/s 0.13‐μm CMOS inductorless transimpedance amplifier with 1 pF input capacitance for optical communications

Parapari

Koozehkanani

et al. 2022

Circuit Theory & Apps

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“…When P=2, the first four Walw(i,t) values are sampled. Four Walgroups [( 5), ( 6), (7), and (8)] are enumerated to form a fourthorder orthogonal matrix (9). (5)…”

Section: B Chord Codingmentioning

confidence: 99%

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication

et al. 2022

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A novel high-speed transceiver based on 7 bit correlated non-return-to-zero(CNRZ-7) with high-bandwidth-density(bandwidth per unit length) and low-power for Die-to-Die(D2D) communication is proposed. In order to further improve the SNR and the bandwidth of the CNRZ-5 in D2D communication, a CNRZ-7 based transmitter matrix and receiver matrix are proposed firstly, which are derived from Walsh Hadamard(W-H) transform and inverse transformation. In addition, to reduce the power consumption of the transmitter, the encoding driver based on CNRZ-7 transmitter matrix is designed with source series terminated drivers(SST). To further improve the SNR of the receiver, the decoding circuit based on CNRZ-7 receiver matrix is designed with a special multi-input comparators(MIC), which contain equalizer circuits. This transceiver is designed with a 28nm CMOS technology and the core area is 0.66mm 2 . The postsimulation results show that this transceiver can operate at 280 Gb/s, and the data rate is 35 Gb/s/wire. The worst width of the receiver's eye-diagrams is 0.45UI when the transceiver operates at a 50 mm PCB channel with a 10dB@20GHz insertion loss, and the total BER is less than 1E-15. The power consumption is 1.1pJ/b under a normal corner.INDEX TERMS Wireline transceiver, correlated non-return-to-zero(CNRZ), Walsh Hadamard, SST, MIC, D2D communication, pin efficiency.

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“…Another recent SerDes trend is the application of four-level pulse-amplitude modulation (PAM-4) [1]- [7], [17]. Compared to non-return-to-zero (NRZ) signaling, PAM-4 signaling reduces the Nyquist frequency of transmitted data by half.…”

Section: Introductionmentioning

confidence: 99%

An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

Wang

Choi

Lee

et al. 2022

IEEE J. Solid-State Circuits

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This article presents a 200-Gb/s pulse amplitudemodulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process.

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8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET

Cited by 53 publications

References 4 publications

A 12.5 Gb/s 0.13‐μm CMOS inductorless transimpedance amplifier with 1 pF input capacitance for optical communications

A 12.5 Gb/s 0.13‐μm CMOS inductorless transimpedance amplifier with 1 pF input capacitance for optical communications

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication

An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

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