8 b 10 MS/s differential SAR ADC in 28 nm CMOS for precise energy measurement

Abstract

In this article an 8-bit differential Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC), designed in the 28 nm CMOS process is presented. It is aimed at pixelated radiation imaging detectors. It allows to distinguish 256 levels of energy and is capable of converting 10 MS/s. The measured INL and DNL are ±0.5 LSB and ±0.3 LSB, respectively. Importantly, the proposed ADC’s comparator offset voltage correction is realized in a time domain allowing to shift the transfer characteristics within the 12 LSB range with no conversion rate degradation. The core of the ADC occupies only 30 µm × 60 µm and the power consumption is 45 µW.

Automated, adaptive, fast reset circuit for wide-energy range detector front-end

“…(10) The low value of Q resets the comparator. (11) The equal levels of both the comparator outputs clear the XOR output. Once the circuit is initially triggered, it continues operating automatically as long as the CSA output voltage is higher than the CSA reference voltage.…”

“…As the reference voltage is also required for the active feedback, it is not considered as an additional circuitry introduced by the reset method. To mitigate the comparator offset issue, the time-domain offset calibration method is used [9][10][11]. The discharging current can be regulated by means of the 5 bit current-steering digital-to-analog converter (DAC).…”