The paper presents the design of the active feedback used in a charge-sensitive amplifier. The predominant advantages of the presented circuit are its ability for setting wide range of pulse-time widths, small silicon area occupation and low power consumption. The feedback also allows sensor leakage current compensation and, thanks to an additional DC amplifier, it minimizes the output DC voltage variations, which is especially important in the DC coupled recording chain and for processes with limited supply voltage. The paper provides feedback description and its operation principle. The proposed circuit was designed in the CMOS 130nm technology.

In this article an 8-bit differential Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC), designed in the 28 nm CMOS process is presented. It is aimed at pixelated radiation imaging detectors. It allows to distinguish 256 levels of energy and is capable of converting 10 MS/s. The measured INL and DNL are ±0.5 LSB and ±0.3 LSB, respectively. Importantly, the proposed ADC’s comparator offset voltage correction is realized in a time domain allowing to shift the transfer characteristics within the 12 LSB range with no conversion rate degradation. The core of the ADC occupies only 30 µm × 60 µm and the power consumption is 45 µW.

In this article, we present a front-end amplifier that is equipped with a precise, fast, and automated reset circuit responsible for two actions: restoring the charge-sensitive amplifier output voltage from a pulse level to baseline, and the analog-to-digital conversion of the pulse amplitude. Importantly, the circuit is self-clocking, which allows to take advantage of the modern submicrometer CMOS process, and thus speed-up the reset and conversion phases. Thanks to the proposed approach, the fast clock signal distribution and an independent analog-to-digital converter per channel are not required, saving both the power consumption and the silicon area. The presented circuitry was adopted into 100-pixel-shaped recording channels and sent for fabrication in the CMOS 28 nm process.

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