8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Kang, U; Chung, Hoeju; Heo, Su-Jeong; Park, Duk-Ha; Lee, Hoon; Kim, Jin Ho; Ahn, Su−Jin; Cha, Sooho; Ahn, Jin Hwan; Kwon, Dukmin; Lee, Jae‐Wook; Joo, Hyonam; Kim, Woo-Seop; Jang, Dongyoung; Kim, Nam Seog; Choi, Jung-Hwan; Chung, Taeyoung; Yoo, Jung-Keun; Choi, Jongwan; Kim, Changhyun; Jun, Young-Hyun

doi:10.1109/jssc.2009.2034408

Cited by 381 publications

(154 citation statements)

References 9 publications

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“…In general, wire pitches shrink faster than modules allowing more wires between modules. This trend of interconnect scaling is reported in many articles [2][3][4][6][7][8][9][10][11][12]. Knickerbocker greatly scaled length and density of interconnects by densely populating chip dies on a silicon substrate package called "silicon carrier" instead of on a PCB [6].…”

Section: Introductionmentioning

confidence: 86%

A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design

Choi¹,

Sim²,

Park³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper explains modeling and analysis of RC-dominant wires for high-speed wireline transceiver design. A closed form formula derived from telegrapher's equation accurately describes a frequency response of an RC-dominant wire, yet it is simple and intuitive for designers to easily understand design trade-offs without a complex numerical equation solver. This paper explains how the model is derived and how it can help designers in example transceiver designs.

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Section: Introductionmentioning

confidence: 86%

A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design

Choi¹,

Sim²,

Park³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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“…The completion data buffer (5) receives the data and generates data for completion. It also does (6) and (7) for transmission by using a packet buffer, and the received data may be checked and interpreted in (8) and (9 The important information for operating the protocol engine's internal buffer is the state of the buffers and whether…”

Section: Controlling Buffersmentioning

confidence: 99%

“…HBM uses the interposer to expand the bandwidth between DRAM and GPU or CPU, and Wide IO also has a stacked structure, and so on. But it is known that there is a problem with the formation and reliability of the TSV and the micro-bump inside a stacked die [8], [9]. Secondly, the decrease of memory latency has been studied to reduce the access delay, which is carried out mainly on SDRAM that has a relatively long latency time.…”

Section: Introductionmentioning

confidence: 99%

Feasibility Test of Protocol Engines for a New Video System in Packet Communication

Kwon¹,

Choi²

2016

IJCTE

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Abstract-The layout between the processor and memory in parallel bus is very complex and difficult to place and route. The expansion of memory capacity and bandwidth is limited. A new memory system using an optical connection is proposed. We designed a serial interface using packet communication, and implemented a protocol engine to be executed on the interface. To test the feasibility of the protocol engine, we implemented a video system using an embedded processor on FPGA. The master and slave protocol engines were on the same FPGA, but used the clock differently. We conducted an experiment on the function of the proposed protocol engine between the video frame buffer and memory using a 2×10-Gbps serial link.Index Terms-Memory channel, protocol, main memory.

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“…An overall reduction in wire length is obtained (about 50 % for certain configurations), resulting into significant reduction in both power and delay [16,18]. A 3D manufactured DRAM based on the stacking of banks manufactured by Samsung is described in [9]. 2.…”

Section: D Memory Architecturesmentioning

confidence: 99%

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Taouil

Hamdioui

2012

J Electron Test

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Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Third, these two parts are integrated to analyze the tradeoff between yield improvement and its associated cost; the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, even at lower cost. For example, for a stack size of six stacked layers and a die yield of 85 %, a relative yield improvement of 118.79 % is obtained with two redundant layers, while this is 14.03 % only with wafer matching. The additional cost due to redundancy pays off; the cost of producing a good 3D stacked memory chip reduces with 37.68 % when using layer redundancy and only with 12.48 % when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields. Finally, layer redundancy and wafer matching are integrated to obtain further cost reductions.

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8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Cited by 381 publications

References 9 publications

A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design

A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design

Feasibility Test of Protocol Engines for a New Video System in Packet Communication

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

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