80 nm 512M DRAM with enhanced data retention time using partially-insulated cell array transistor (PiCAT)

Abstract

An 80 nm 512M DDR DRAM with partially-insulated cell array transistor (PiCAT) was fabricated. SilSiGc cpitaxial growth and selective SiGe etch process were used to form PiOX (Partiallyinsulating Oxide) under source and drain of the cell transistor. Using these technologies, partial-SO1 (Silicon-On-lnsulator) Structure could be realized with excellent Structural and electrical advantages on bulk Si wafer. Self-limited shallow junction under sourceldrain and halo doping effect at the channel region were formed by PiOX. With PiCAT, junction leakagc current and SCE (Short Channel Effect) were reduced, and excellent data retention time was obtained.

Fully Integrated Advanced Bulk FinFETs Architecture Featuring Partially-Insulating Technique for DRAM Cell Application of 40nm Generation and Beyond

“…Cell array transistors are made on bulk FinFETs featuring partially insulating oxide layers, while peripheral and core transistors are made on epi-Si. PI-FinFETs are formed by the processes in Fig.1 (7). After inserting partially insulated layers (PIOX) under S/D, we fabricated bulk FinFETs by using a local damascene scheme (5).…”

Reliability Investigations for Bulk-FinFETs Implementing Partially-Insulating Layer

“…Recently, there was an attempt to implement partially-insulating layers under the source / drain (PiFETs) to reduce short channel effect and junction areas [3][4]. Some outstanding results were reported in those researches that SCE immunities were improved by self-induced halo region and self-limiting S/D shallow junction.…”