84 dB DC‐gain two‐stage class‐AB OTA

Anisheh, Seyed Mahmoud; Abbasizadeh, Hamed; Shamsi, Hossein; Dadkhah, Chitra; Lee, Kang-Yoon

doi:10.1049/iet-cds.2018.5038

Cited by 16 publications

(5 citation statements)

References 40 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It can be observed that this design intimates an impressive improvement in FOM SR and g UGB, which allows a more expedient trade-off between speed, power, and load in [28]. This work also exhibits more remarkable small-signal driving ability than [26,[29][30][31][33][34][35] though lower than [27,28,32].…”

Section: Discussion and Comparisonmentioning

confidence: 80%

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

Ghosh

Bhadauria

2021

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

An efficient architecture of a high-performance ultra-low-voltage gate-driven two-stage pseudo-fully differential operational transconductance amplifier (OTA) is presented. The proposed subthreshold-region operated OTA utilizes two identical conventional current-mirror-based source coupled pseudo-differential amplifiers with their cross-connected gate as core amplifier blocks. The input core differential pair exploiting forward body terminal biasing scheme at output load employed in cascaded stages essentially improves the overall transconductance more than twice compared to the conventional pseudo-differential pair based OTA and achieves near rail-to-rail output voltage swing (90.2% of supply voltage) for near rail-to-rail input common-mode voltage (94.92% of supply voltage). The circuit is designed and optimized using g m /I D technique associated with the Particle Swarm Optimization (PSO) algorithm with a single supply of 0.35 V for a capacitive load of 10 pF and simulated in Cadence Virtuoso analog environment using UMC 180-nm CMOS technology. Post-layout simulations have been accomplished to justify the performance of the proposed OTA. It achieves an open-loop gain of 83.00 dB, phase margin of 61.48°, and power dissipation of 35.04 nW at a unity gain frequency of 24.78 kHz. A low-frequency continuous second-order G m -C filter is also implemented to validate its workability. Simulation results of this work are compared to the state-of-the-art architecture available, and enhanced performance is validated. Keywords Operational transconductance amplifier (OTA) Á Unity gain frequency (UGF) Á Subthreshold region Á Input common-mode range (ICMR) Á Biquad G m -C filter & Sougata Ghosh

show abstract

Section: Discussion and Comparisonmentioning

confidence: 80%

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

Ghosh

Bhadauria

2021

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…To re-position ωZ1 according to Eqn. (11), one can increase the value of RC. As a result, the impact of modifying the R-C compensation network, compared to the conventional design, is shown in the ideal open-loop response of Fig.…”

Section: Amentioning

confidence: 99%

Conventional CMOS OTAs Driving nF-Range Capacitive Loads

Mohammed

Roberts

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

This work introduces a new design technique for extending the load driving capability of conventional Miller-RC CMOS OTAs, up to nF-range capacitive loads (CL), with nearoptimum small-and large-signal time responses. The proposed technique involves modifying the R-C compensation network such that the unity-gain frequency, t, of the OTA is highly increased. This additional increase in ωt can then be traded-off for higher loads by transferring the dependency of the dominant pole to CL. To implement and verify the proposed technique, the classical differential-ended two-stage OTA was used as a design example in order to drive a load of 1000 pF. Interestingly, with the modified compensation network, an area efficient design was achieved, demonstrating excellent performance.

show abstract

“…MOEA/D is implemented in MATLAB R2016b version and is tested on Intel corei5-4460 CPU @ 3.2 GHz with 16 GB RAM. Operational amplifiers (op-amps) can be considered as an essential block in many mixedmode systems [39][40][41][42].The proposed method is applied to three-stage amplifier and two-stage class-AB operational trans-conductance amplifier (OTA).…”

Section: Performance Evaluationmentioning

confidence: 99%

“…Two-stage class-AB OTAIn Ref[41], a two-stage class-AB OTA is suggested. By increasing the trans-conductance of the first stage, DCgain is enhanced.…”

mentioning

confidence: 99%

A Placement and Routing Method for Layout Generation of CMOS Operational Amplifiers Using Multi-Objective Evolutionary Algorithm Based on Decomposition

2021

View full text Add to dashboard Cite

This paper presents a new placement and routing method for layout generation of CMOS operational amplifiers (op-amps). Both circuit sizing and layout generation stages are performed automatically. In the proposed method, layout effects are considered during the layout generation. Layout parasitics and geometry information are extracted from a new automated layout generator. In this method, the multi-objective evolutionary algorithm based on decomposition (MOEA/D) is used as an optimization algorithm. In order to verify the performance of the proposed method, the design of three-stage operational amplifier (op-amp) and two-stage class-AB operational trans-conductance amplifier (OTA) in a 0.18µm process CMOS technology with 1.8 V supply voltage are presented. The simulation results indicate the efficiency of the proposed analog layout generation method.

show abstract

84 dB DC‐gain two‐stage class‐AB OTA

Cited by 16 publications

References 40 publications

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

Conventional CMOS OTAs Driving nF-Range Capacitive Loads

A Placement and Routing Method for Layout Generation of CMOS Operational Amplifiers Using Multi-Objective Evolutionary Algorithm Based on Decomposition

Contact Info

Product

Resources

About