This study presents a new placement and routing method for analogue integrated circuit layout generation based on an evolutionary algorithm, which is called modified cuckoo optimisation algorithm. Layout parasitic effects are taken into account to ensure that the performance of the circuit is not deteriorated. In order to verify the performance of the proposed method, layouts of three different circuits including differential to single-ended amplification stage, two-stage and three-stage operational amplifiers (op-amps) are automatically generated in a 0.18 μm CMOS process with a 1.8 V supply voltage. The simulation results show the efficiency of the proposed algorithm in the analog layout generation.

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Signal analysis tools such as Fourier transform are often applicable on data with a limited length. Segmentation is an important pre-processing step in many signal processing applications. Statistical characteristics of the signal in a segment are often preferred to be similar. This characteristic, stationarity, improves performance of signal analysis technique. This article develops an adaptive segmentation method based on wavelet transform and fractal dimension from two aspects. One is to use discrete stationary wavelet transform in pre-processing step instead of using classical wavelet transform. The other is to choose the optimal parameters. Two parameters are needed to calculate the fractal dimension of a decomposed signal, window length and percentage overlapping of the successive windows, which affect the performance of the proposed approach. These parameters are optimally set using the particle swarm optimisation algorithm. Performance of the proposed method is compared with three other existing segmentation methods using both synthetic signal and real data. The results indicate the superiority of the proposed technique in terms of accuracy compared to existing methods.

Operational trans-conductance amplifiers (OTAs) are an essential building block in analogue and mixed-signal circuits. In this study, a new two-stage class-AB OTA is proposed. The class-AB operation is obtained without extra power dissipation, and without unity-gain bandwidth or noise degradation. The circuit was fabricated using 1P6M 180-nm CMOS technology under 1.8 V supply voltage. The measurement results indicate 13 dB enhancement in DC-gain and 1.8 times improvement in slew rate compared to its conventional counterpart. Comparison results indicate that the proposed OTA demonstrates better performance than the state-of-the-art designs.

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