85% endurance error reduction and data-retention lifetime enhancement by changing the reset voltage in 40 nm TaO _X -based ReRAM

Abstract

This paper proposes a changing reset voltage technique for 40 nm TaOX-based resistive random access memories (ReRAM). In the proposed technique, reset voltage (VRESET) changes at high endurance such as 104 set/reset cycles. The changing reset voltage technique decreases the measured total bit-error rate (BER) of both the low resistance state (LRS) and high resistance state (HRS) by 85%, compared with conventional fixed reset voltage. In addition, the current difference between LRS and HRS at probability = 50% (window) increases by 57% with the proposed technique, which increases the read margin between set and reset. Moreover, by decreasing the tail bits and expanding the read margin, the data-retention lifetime is increased. As a result, the changing reset voltage technique is recommended for high endurance and long data retention lifetime. Finally, this paper proposes a physical model of the proposed technique.

97.6% array area reduction, ReRAM computation-in-memory with hyperparameter optimization based on memory bit-error rate and bit precision of log-encoding simulated annealing

“…3,16) In terms of a ReRAM device, on the one hand, a ReRAM device has reliability issues because ReRAM causes bit-error at high Set/Reset cycles. 15,17,18) On the other hand, as for biterror in SA, it has been reported that searching the optimal answer by controlling the device noise properly is more accurate. 13) Therefore, by co-design of a ReRAM device and log-encoding SA, the influence of the asymmetric ReRAM error characteristics and bit precision on SA is analyzed.…”