8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing

Abstract

Large scale digital computing almost exclusively relies on the von-Neumann architecture which comprises of separate units for storage and computations. The energy expensive transfer of data from the memory units to the computing cores results in the well-known von-Neumann bottleneck. Various approaches aimed towards bypassing the von-Neumann bottleneck are being extensively explored in the literature. These include in-memory computing based on CMOS and beyond CMOS technologies, wherein by making modifications to the memory array, vector computations can be carried out as close to the memory units as possible. Interestingly, in-memory techniques based on CMOS technology are of special importance due to the ubiquitous presence of field-effect transistors and the resultant ease of large scale manufacturing and commercialization. On the other hand, perhaps the most important computation required for applications like machine-learning etc. comprises of the dot product operation. Emerging non-volatile memristive technologies have been shown to be very efficient in computing analog dot products in an in-situ fashion. The memristive analog computation of the dot product results in much faster operation as opposed to digital vector in-memory bit-wise Boolean computations. However, challenges with respect to large scale manufacturing coupled with the limited endurance of memristors have hindered rapid commercialization of memristive based computing solutions. In this work, we show that the standard 8 transistor (8T) digital SRAM array can be configured as an analog-like in-memory multi-bit dot product engine. By applying appropriate analog voltages to the read-ports of the 8T SRAM array, and sensing the output current, an approximate analog-digital dot-product engine can be implemented. We present two different configurations for enabling multi-bit dot product computations in the 8T SRAM cell array, without modifying the standard bit-cell structure. We also demonstrate the robustness of the present proposal in presence of non-idealities like the effect of line-resistances and transistor threshold voltage variations. Since our proposal preserves the standard 8T-SRAM array structure, it can be used as a storage element with standard read-write instructions, and also as an on-demand analog-like dot product accelerator.

Photonic In-Memory Computing Primitive for Spiking Neural Networks Using Phase-Change Materials

“…The initial efforts [4][5][6] in hardware implementations of SNNs was based on standard von-Neumann architecture [7] based on Complementary Metal Oxide Seminconductor (CMOS) technology where the synaptic units of the neural networks are stored in the digital memory and * ichakra@purdue.edu repeatedly fetched by the processor for computing operations. However, the overhead of frequent data transport between the memory and processor have led to a shift in the computing paradigm as 'in-memory' computing platforms [8,9] attempt to emulate the 'massively parallel' operations of the brain. Although the term 'neuromorphic' was primarily coined [10] with CMOS technology in mind, this computing domain has branched out to nonvolatile memory (NVM) technologies such as oxide-based memristors [11], spintronics [12], phase change materials (PCM) [13,14], etc in the recent years.…”

Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays

“…This opens pathways for adopting new simplified binary in-memory computing paradigms for accelerating neural networks. As shown in [15]- [17], bit-wise Boolean operations including XORs or XNORs as well as non-Boolean vectormatrix dot-products can easily be incorporated within standard SRAM arrays. Such SRAM based in-memory computations open up new possibilities of augmenting the existing memory arrays with compute capabilities.…”

X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories

“…Moreover, we go a step further and propose the novel 'read-compute-store' scheme, where the computed result can be stored in-situ, within the memory array, without the need for latching the result and performing a subsequent memory-write instruction. In addition, recently memristor like multi-bit dot product computations using 8T cells has been proposed in [10]. The present works differs from the work in [10] since the computations presented in [10] are analog-like computations in SRAM arrays and requires more complex peripheral circuitry, whereas the focus of the present work is purely digital vector computations in the SRAM arrays.…”