90 GHz f/sub T/ SiGe HFET with fully optical self-aligned sub 100 nm gate

Abstract

Advanced material properties and sophisticated layer structures of SiGe hetero field-effect transistors are the basis for expected [ I ] and partly demonstrated elevated RF and noise performance of these devices [2]. However, a lack of lateral device optimization, due to lithography restrains and non self-aligned technology processes often limits the electrical performance of these transistors.Self-aligned technology concepts for hetero field-effect transistors often fail because of the incompatibility between metal gates and high temperature process steps. The new fully optical, selfaligned integration concept presented here uses a replacement-gate structure to overcome this problem ( Fig. 1). In contrast to conventional SiGe HFET technologies, which apply e-beam lithography the dummy-gate structure is defined optically. Polyimide is utilized as the favored dummygate material, because it is easy to handle by spin on, has a high temperature stability and is removable without damages from the heterostructure. The replacement gate acts as a mask for the selfaligned sourceidrain implantation and the low ohmic Ni salicidation of the contacts. The final physical gate length is achieved by a dry etching plasma step, which shrinks the polyimide to sub 100 nm dimensions (Fig. 2). Then Si02 passivation takes place and a planarization process ensures a flat device topography. With an isotropic etch-back step the replacement-gate is revealed again for wet chemical removal. After rapid thermal annealing at 600 "C for 30 s, Pt/Ti evaporation forms a Schottky-contact at the bottom of the gate trench. The following Au electroplating process is the best choice to fill the high aspect ratio gate trench and to deposit a thick homogenous metallization layer. In a final etching step the metallization layer is patterned and the size of the gate head is defined independently from the gate-length L , . The flexibility of this technology concept allows also the realization of a MOS-or pn-junction HFET with only slight changes in the process flow and it is even applicable for IIW HEMTs. Fig. 3 shows the transfer characteristic of a 90 nm gate-length device. An outstanding result is the high extrinsic transconductance g, with a maximum value of 685 mWmm (gmi = 882 mS/mm) at a gate bias of 0.2 V. Furthermore the transistor exhibits an elevated Ion/I0f ratio of 5 1 .2*103 and an excellent pinch-off behavior. Considering the ID(VDs)-curves we find a large saturation current beyond 500 mA/mm at VDS = 1.5 V and VG = 0.7 V (Fig. 4) and a high breakdown voltage of about 4.0 V S-parameters were measured on-wafer in the range from 2 to 50 GHz. The deembedded highest fT was found to be 90 GHz for the 90 nm device (Fig. 5). Compared to the best results of the conventional technology an enhancement of around 20 % was achieved (Fig. 6). The obtained g, and fs results are the highest values reported so far for SiGe n-HFET [3], [4]. Distinctly higher frequencies are expected for a SiGe MOS version, which allows L,, towards zero.

SiGe virtual substrate HMOS transistor for analogue applications

“…And last, but not least, SiGe HMOS transistors have a huge potential in the fields of RF analogue electronics and micropower applications. The research has benefited a lot from the advances in SiGe heterojunction FETs (HFETs) [4], where n-channel devices have figures of merit comparable to similar geometry GaAs transistors. It is emphasised here, that these devices too have buried channels (but not a gate oxide).…”

Average Drift Mobility and Apparent Sheet-Electron Density Profiles in Strained-Si–SiGe Buried-Channel Depletion-Mode n-MOSFETs

“…1, the measured total gate capacitance can be expressed as a series combination of the oxide capacitance , which is independent of the applied vertical bias and an effective junction capacitance , which is bias dependent [4] (1) is calculated at the highly positive gate bias limit, where all charge is attracted to the gate oxide interface, where be- comes infinite and equals the total measured capacitance. From (1) we get (2) The introduced effective capacitance is assumed to be an ideal junction capacitance, which follows Schottkys depletion approximation (i.e., the Debye length is equal to zero) and involves all active layers contained between the gate oxide and the virtual substrate. In this respect, the physical location of the upper plate of is fixed at the interface between the gate-oxide and the semiconductor.…”

“…These are enhancement-mode (EM) devices and have surface channels (SC). But there is little found in the literature on their depletion-mode (DM) buried-channel (BC) counterparts, despite the fact that they too can share the convenience of a standard Si MOS process, and despite the advances in n-type strained-Si-SiGe modulation-doped field effect transistors (MODFETs), where cutoff frequencies in the range of 90 GHz have been reported [2]. In BC MOSFET, the semiconductor heterostructure contains multiple layers, with the carriers not always confined in the intended strained-Si channel, and the most relevant approach is to evaluate the free carrier density and the drift mobility profiles with the depth and/or with the vertical effective field and the applied gate bias.…”

SiGe HMOSFET monolithic inverting current mirror

“…Briefly, the heterostructure is grown on a SiGe "virtual substrate" [3] by molecular beam epitaxy (MBE). Then, the sites of the transistors constituting the current mirror are electrically Depletion mode transistors are often required in analogue circuits, where a "normallyon" state is achieved without additional biasing.…”

“…They represent a trend in non-classical CMOS and band-engineered transistors [2], they are compatible with the existing silicon fabrication lines and are bound to dominate the market in the near future. Given this and paying attention to the recent advances in heterojunction strained-silicon modulation-doped FETs (HMODFETs) [3], one has to realise that it is only a matter of time before buried-channel depletion-mode Si/SiGe heterojunction MOSFETs (HMOSFETs) also make their presence strongly felt. Despite this, not much has been published on such devices or, indeed, circuits.…”