2014 Symposium on VLSI Circuits Digest of Technical Papers 2014
DOI: 10.1109/vlsic.2014.6858449
|View full text |Cite
|
Sign up to set email alerts
|

92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
8
0

Year Published

2015
2015
2018
2018

Publication Types

Select...
5
1

Relationship

1
5

Authors

Journals

citations
Cited by 9 publications
(8 citation statements)
references
References 0 publications
0
8
0
Order By: Relevance
“…For example, the output impedance, r o is high, for an off‐chip transconductor ( g m ). The resistance R D works as a filter and it is much smaller than R F [7, 23]. If C e = ( C 1 C 2 /( C 1 + C 2 )) is much higher than the parasitic parallel capacitor, C o of a crystal, the oscillation frequency is approximately given by [23] ωnormalo=1LCe where L is the equivalent inductance of the crystal.…”
Section: Application Of the Power Generation Methods For Off‐chip Crysmentioning
confidence: 99%
See 3 more Smart Citations
“…For example, the output impedance, r o is high, for an off‐chip transconductor ( g m ). The resistance R D works as a filter and it is much smaller than R F [7, 23]. If C e = ( C 1 C 2 /( C 1 + C 2 )) is much higher than the parasitic parallel capacitor, C o of a crystal, the oscillation frequency is approximately given by [23] ωnormalo=1LCe where L is the equivalent inductance of the crystal.…”
Section: Application Of the Power Generation Methods For Off‐chip Crysmentioning
confidence: 99%
“…The proposed analysis approach was validated by designing a crystal oscillator for low power WSN applications. The following design specifications were chosen to closely match [7]: † Oscillation frequency: 39 MHz. † Supply voltage: 1 V. † Start-up time: <2.5 μs.…”
Section: Design Examplementioning
confidence: 99%
See 2 more Smart Citations
“…In contrast, in the stateof-the-art design, many different f CLK 's, V DD 's, and V TH 's are used within a chip and they are dynamically changed to minimize the energy. Such temporal-spatial fine-grained control includes the dynamic voltage scaling [2], the dynamic frequency scaling [3], the power gating, the clock gating, the body biasing, the local gate overdrive [4], and the quick wakeup circuits [5]. converter, logic circuits, SRAM, and RF circuits for the temporal-spatial fine-grained control to minimize the energy.…”
Section: Energy Efficient Designmentioning
confidence: 99%