98-dB Gain Class-AB OTA With 100 pF Load Capacitor in 180-nm Digital CMOS Process

Anisheh, Seyed Mahmoud; Abbasizadeh, Hamed; Shamsi, Hossein; Dadkhah, Chitra; Lee, Kang-Yoon

doi:10.1109/access.2019.2896089

Cited by 29 publications

(13 citation statements)

References 29 publications

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“…It can be observed from Table 5 that Kulej and Khateb 53 proposed 2‐stage Miller OTA which shows gain , GBW , IRN and power consumption of 67.3 dB, 3 kHz, 1.85 μV/√Hz @ 1 kHz, and 0.015 μW, respectively. Anisheh et al 54 proposed 2‐stage class‐AB OTA that delivers gain, GBW , IRN and power consumption of 98 dB, 21 000 kHz, 0.25 μV/√Hz @ 100 kHz, and 3000 μW, respectively. Further, Baghtash et al 3 proposed BD push‐pull OTA which delivers gain , GBW , IRN and power consumption of 81.37 dB, 280.4 kHz, 0.213 μV/√Hz @ 1 kHz, and 0.3 μW, respectively.…”

Section: Resultsmentioning

confidence: 99%

Design of low‐voltage low‐noise operational transconductance amplifiers for low frequency applications

Sharma,

Kumar,

Madan

et al. 2024

Int J Numerical Modelling

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Low‐noise and low‐voltage operation is prime requirement of an operational transconductance amplifier for low frequency applications. However, achieving low‐noise operation at low supply voltages is a challenging task in CMOS technology owing to noise‐power and noise‐stability tradeoffs. This article outlines, the design of four differential bias self‐cascode (DBSC) operational transconductance amplifiers (OTAs) working at ±0.7 V. The four design techniques namely gate driven (GD), bulk driven (BD), bulk driven quasi‐floating gate (BDQFG), and gate driven quasi floating bulk (GDQFB) have been applied on DBSC OTAs. The designing aspects and performance parameters of these four OTAs such as gain, gain‐bandwidth, input referred noise (IRN), settling time (ST), common mode rejection ratio (CMRR), total harmonic distortion, input impedance, transconductance, power consumption, area consumption and process/mismatch variations have been fairly compared in this work. These DBSC OTAs have been designed and simulated using a standard 0.18‐μm 6M1P CMOS N‐well process. The results infer GD DBSC OTA shows high CMRR of 125.83 dB. While the BD DBSC OTA consumes very low power of 0.2 μW. The BDQFG DBSC OTA shows low 1% ST of 24.83 μS. The GDQFB DBSC OTA show high transconductance (2.35 mS), high gain (64.97 dB), and low IRN (0.40 μV/√Hz at 10 Hz). The theoretical predictions for these OTAs agree with the post‐layout simulations. The proposed OTAs can be used for designing various analog circuits such as programmable gain amplifiers, variable gain amplifiers, and transimpedance amplifiers for low‐frequency biomedical and health care applications.

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Section: Resultsmentioning

confidence: 99%

Design of low‐voltage low‐noise operational transconductance amplifiers for low frequency applications

Sharma,

Kumar,

Madan

et al. 2024

Int J Numerical Modelling

View full text Add to dashboard Cite

show abstract

“…To demonstrate the performance of the proposed algorithm, it is tested on a two‐stage class‐AB OTA shown in Figure 5 [27]. The common mode feedback circuit and Bias circuit are shown in Figure 6 and Figure 7 respectively.…”

Section: Simulation Resultsmentioning

confidence: 99%

A four‐stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms

Yaseri

Maghami

Radmehr

2022

IET Computers & Digital Tech

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A high yield estimation is necessary for designing analogue integrated circuits. In the Monte‐Carlo (MC) method, many transistor‐level simulations should be performed to obtain the desired result. Therefore, some methods are needed to be combined with MC simulations to reach high yield with high speed at the same time. In this paper, a four‐stage yield optimisation approach is presented, which employs computational intelligence to accelerate yield estimation without losing accuracy. Firstly, the designs that met the desired characteristics are provided using critical analysis (CA). The aim of utilising CA is to avoid unnecessary MC simulations repeating for non‐critical solutions. Then in the second and third stages, the shuffled frog‐leaping algorithm and the Non‐dominated Sorting Genetic Algorithm‐III are proposed to improve the performance. Finally, MC simulations are performed to present the final result. The yield value obtained from the simulation results for two‐stage class‐AB Operational Transconductance Amplifer (OTA) in 180 nm Complementary Metal‐Oxide‐Semiconductor (CMOS) technology is 99.85%. The proposed method has less computational effort and high accuracy than the MC‐based approaches. Another advantage of using CA is that the initial population of multi‐objective optimisation algorithms will no longer be random. Simulation results prove the efficiency of the proposed technique.

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“…Table 1 shows the types and specification of EEG is used to record the complex signal activity of the brain from various locations on the scalp [6]- [8]. Nowadays, there are multiple brain imaging techniques including functional magnetic resonance imaging (fMRI) [9] which are superior noninvasive alternative tests used to diagnose medical conditions of the brain, but for portable monitoring we still consider EEG to be the best alternative [10]. For regular monitoring using EEG, there is a need to design a fully integrated LPF with fc below 70 Hz [11] meeting performance specifications of reduced silicon area, better noise immunity, high dynamic range, and lower power consumption.…”

Section: Figure 1 Block Diagram Of Analog Front End Processing Circuitmentioning

confidence: 99%

Low power CMOS Gm-C based low pass filter for front end neural signal processing

Dixit,

Srivastava,

Kumar

et al. 2024

IJPEDS

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The sub 100 µV voltage levels and sub 100 Hz frequency range makes the processing of most popular signal electroencephalograph (EEG) for brain functionality analysis, a complex task. The low frequency content of EEG (useful signals below 70 Hz) is commonly used for diagnosis of various brain related disorders making low-pass filter (LPF) a key block in front-end processing as noise reduction and resolution enhancement is crucial for precise recovery of these information. This paper is aimed to design reduced transconductance (Gm) based low power and small area CMOS LPF with cutoff frequency (fc) around 70 Hz. The proposed design is simulated using Cadence virtuoso tool and gives cut-off frequency of 72.958 Hz with low output noise of 3.0609 µV/√Hz and power consumption of 264.060 nW at operating voltage of 0.4 V. The simulation results show linearity of performance over -40 to 100 °C. Layout of circuit takes up area of 86.74×81.21 µm and post layout simulation shows 5% variation in power consumption as compared to pre layout simulations.

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98-dB Gain Class-AB OTA With 100 pF Load Capacitor in 180-nm Digital CMOS Process

Cited by 29 publications

References 29 publications

Design of low‐voltage low‐noise operational transconductance amplifiers for low frequency applications

Design of low‐voltage low‐noise operational transconductance amplifiers for low frequency applications

A four‐stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms

Low power CMOS Gm-C based low pass filter for front end neural signal processing

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