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This paper 1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs coarse-grain VLSI cells with high functionality, performance, and reconfigurability. The advantages of this approach are high performance, small area and low power compared to FPGAs, and greater flexibility over ASICs. Moreover, many of the advanced algorithms, including the independent component analysis, can be systolically mapped to it. The paper discusses these coarse-grain cells in light of a new concept, namely multi-granularity, which simultaneously facilitates defect tolerance and reconfigurability. In particular, it is shown that the multipliers in these J-platform cells can benefit from an innovative block. Called multiplier building block (MBB), it can be used for defect tolerance as well as for configuring larger multipliers, thereby enhancing the yield and computational flexibility. An application example relating to defect tolerant visible sensors is described. We also discuss energy economization through the use of sleep transistor networks and multi-hop communication. The ultimate goal is to build such 3-D heterogeneous sensor nodes with integrated processing and communications capability, and with provision for defect tolerance on the sensor plane as well as the multiple processing planes.

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Defect Tolerance for a Capacitance Based Nanoscale Biosensor

Chapman

Jain

2008

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

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Cited by 11 publications

References 14 publications

Citrus greening detection using visible spectrum imaging and C-SVC

Citrus greening detection using visible spectrum imaging and C-SVC

Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC

Defect Tolerance for a Capacitance Based Nanoscale Biosensor

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