A compact fast elliptic curve scalar multiplier with variable key size is implemented as a coprocessor with a Xilinx FPGA. This implementation utilizes the internal SRAM/registers of the FPGA and has the whole scalar multiplier implemented within a single FPGA chip. The compact design helps reduce the overhead and limitations associated with data transfer between FPGA and host, and thus leads to high performance. The experimental data from the mappings over small fields shows that the carefully constructed hardware architecture is regular and has high CLB utilization.

Several advanced DSP algorithms, arising in applications such as wireless communications, computer graphics, computerized tomography, and speech compression, require extensive use of nonlinear functions. We discuss a new hardware approach to high-speed computation of nonlinear functions. With this approach all of the functions needed can be regularized into a single efficient algorithm. Further, highly reduced cycle implementations can be achieved. Specifically, for real arguments, a new result can be produced every cycle --in a pipelined malde. The underlying principle which has made the combined goals of high-speed and multi-finctionalily possible is significancebased polynomial interpolation of very small ROM tables. Considered are the following seven functions: arctangent, cosine, logarithm, reciprocal, reciprocal-square-root, sine, and square-root.Also presented is a theoretical development for error prediction, a tool for the selection of architectural parameters. Finally, the paper presents a novel technique, named here as 'microshaping', for avoiding overflows, thereby eliminating exception handling.

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