A 0.008‐mm², 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

Abstract

SummaryThis paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm2. The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.

Time‐to‐digital converters—A comprehensive review

“…The input Vin for dual‐slope ADC is generated by charge pump‐based TAC. Similar architecture implemented in Kim et al 29 and reached a fine resolution of 8.87 ps. Using successive approximation register (SAR) ADC for indirect measurement, 30 nearly 1‐ps resolution is reported.…”

An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all‐digital time‐based quantization

“…Digital time‐based quantizers are mostly implemented by delay lines, a chain of delay cells, as will be discussed further in next sections. The basic idea behind time‐based quantization is to translate the analog input voltage into time instances, usually delay of delay cells . In most of all‐digital time‐based quantizers, the analog input voltage is converted to delay of delay cells or sampling pulse of the delay line through additional elements .…”

“…The basic idea behind time-based quantization is to translate the analog input voltage into time instances, usually delay of delay cells. 2 In most of all-digital time-based quantizers, the analog input voltage is converted to delay of delay cells or sampling pulse of the delay line through additional elements. 3,4 To this end, a common approach is to inject a voltage-controlled current to the charging/discharging nodes of the delay cell.…”

Run‐time calibration scheme for the implementation of a robust field‐programmable gate array–based time‐to‐digital converter

“…Time-to-digital converters (TDCs) measure time intervals for various scientific and engineering applications, such as positron emission tomography (PET) scanners, [1][2][3] time-of-flight PET, 4,5 time-of-flight laser radar, 6 and mass spectrometry. [8][9][10][11][12][13][14][15][16] Although the time resolution achieved using a TDC with an ASIC is superior to that achieved using field-programmable gate array (FPGA) platforms, [8][9][10] TDC circuits have been implemented in FPGA platforms due to their flexible and short establishment time. [8][9][10][11][12][13][14][15][16] Although the time resolution achieved using a TDC with an ASIC is superior to that achieved using field-programmable gate array (FPGA) platforms, [8][9][10] TDC circuits have been implemented in FPGA platforms due to their flexible and short establishment time.…”

“…7 TDCs have been implemented in the analog domain by using application-specific integrated circuits (ASICs) capable of providing high time resolution. [8][9][10][11][12][13][14][15][16] Although the time resolution achieved using a TDC with an ASIC is superior to that achieved using field-programmable gate array (FPGA) platforms, [8][9][10] TDC circuits have been implemented in FPGA platforms due to their flexible and short establishment time. Thus, numerous FPGA-based TDCs have been proposed recently.…”