Run‐time calibration scheme for the implementation of a robust field‐programmable gate array–based time‐to‐digital converter

Abstract

In this study, we propose a robust field-programmable gate array (FPGA)-based time-to-digital converter (TDC) with run-time calibration. A code density test was used for differential nonlinearity (DNL) calibration to deal with nonuniformity in delay cells. The proposed calibration scheme is implemented as a four-step finite state machine (FSM) for run-time calibration. We implemented the TDC with the proposed run-time calibration circuit on the Xilinx 65-nm FPGA platform. This improved the DNL and integral nonlinearity (INL) values over those obtained using a TDC without run-time calibration circuit. The DNL and INL values at a time resolution of 46.875 picoseconds were [−0.68, 1.04] and [−4.27, 2.27] least significant bits, respectively. More than 30% DNL and INL improvements are achieved for the TDC with calibration circuit. The results obtained at temperatures of 27 • C to approximately 70 • C indicated that the proposed run-time calibration circuit enhanced the capability of the FPGA-based TDC against temperature effects. The FPGA-based TDC with the proposed run-time calibration FSM provides robust high-resolution performance suited for a range of scientific applications. KEYWORDS differential nonlinearity (DNL), field-programmable gate array (FPGA), run-time calibration, time-to-digital converter (TDC) Int J Circ Theor Appl. 2019;47:19-31.wileyonlinelibrary.com/journal/cta

Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

“…Thus, that scheme cannot calibrate the uniform delay cell immediately in a run-time conversion. Unlike off-line methods, such as that proposed in [29], we adopted a statistical approach to the calibration of an FPGA-based TDC [30] to address the topic of time linearity in real time.…”

“…Therefore, the authors proposed a dual-sampling TDL architecture and a bin decimation method for Xilinx UltraScale FPGAs that could make the delay elements as small and uniform as possible, so that the implemented TDCs can achieve high time resolutions beyond the intrinsic cell delay [23,24]. Recently, selected, divided, or interpolated versions of the delay bin have become more popular to manage the nonuniform delay cells in FPGA-based TDCs, and thus to improve the time resolution and time linearity [22][23][24][25][26][27][28][29][30][31].…”

“…Although such methods enable high time resolution, the designs are highly complex. Nonetheless, time histogram bin counts have been used to calibrate nonlinearity in TDL-TDC delay bins [26][27][28][29][30][31], and two-sample-sums and two-sample-differences of a quantized histogram can be used to minimize the influence of nonlinear quantization on the histogram [26]. Unfortunately, the quantization-and-nonlinearity minimization method depends on a highly complex mathematical analysis [26].…”

“…Nonetheless, that nonlinearity correction was still processed in the same manner as an off-line program-based correction. In [30], the auto-calibration circuit was implemented in a single FPGA; however, the calibration was only run when the FPGA was started. This underlines the importance of developing a straightforward system that can be used to implement run-time corrections to resist environmental effects.…”

“…During a temperature shift from 10-50 • C, their TDC with on-the-fly calibration maintained a 12.8-ps root-mean-squared (RMS) standard uncertainty [31]. Several works have presented delay cells that are sensitive to environmental changes, especially temperature effects [13,14,16,19,23,24,30,31]. Moreover, a comparison is listed in Table 1, which presents the performance of the proposed DDL-TDC compared with existing works.…”