Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

Abstract

This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the proposed DDL-TDC measures the statistical distribution of delays to permit the calibration of nonuniform delay cells in FPGA-based TDC designs. DDLs are also used to set up alternate calibrations, thus enabling environmental effects to be immediately accounted for. Experimental results revealed that relative to a conventional TDL-TDC, the proposed DDL-TDC reduced the maximum differential nonlinearity by 26% and the integral nonlinearity by 30%. A root-mean-squared value of 32 ps was measured by inputting the constant delay source into the proposed DDL-TDC. The proposed scheme also maintained excellent linearity across a range of temperatures.

Efficient Time-to-Digital Converters in 20 nm FPGAs With Wave Union Methods

“…This paper proposed four new TDC architectures with the sub-TDL topology: DS, WU, DSWU and binned-DSWU TDCs. Different from previously reported studies [19], [41]- [43], we concluded that the WU method is still efficient in improving the resolution with maintained linearity in UltraScale FPGAs when the sub-TDL structure is also integrated. By combining the DS structure, the WU method and the sub-TDL architecture, a DSWU TDC with 1.23 ps resolution was implemented and evaluated.…”

“…Unable to effectively solve bubble problems, Wang and Liu concluded that WU methods are not suitable for UltraScale FPGAs [19]. This conclusion has many followers (including us previously) [41]- [43], making the FPGA-TDC community believe that the WU method is not suitable for UltraScale FPGA devices. Therefore, since then, there is no efficient WU TDC reported in UltraScale FPGAs.…”

An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

“…However, these methods require a temperature sensor and a regulating device and require intensive experiments to be performed to determine the relationship between the temperature and the correction parameters. The technology of dual delay lines (DDLs) is used to enable real-time calibrations in [19], which sets up an alternate result of calibrations to offset environmental effects. However, calibrating continuously results in the large power consumption, and the use of DDLs and the double backup of calibration results will consume lots of FPGA resources.…”

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

“…Time-to-digital converters (TDCs) are crucial components in scientific applications [1][2][3], such as positron emission tomography (PET) [4][5][6][7][8][9], time-of-flight (TOF) image sensors [9,10], and light detection and ranging (LiDAR) [11][12][13][14]. For the application of TOF-PET [7][8][9]15,16], it can determine the position accurately by measuring the time difference between the tracer within the response line, and the multi-channel TDCs are required for measuring the time difference accurately to reconstruct the images.…”

“…In general, the measured integral nonlinearity (INL) and differential nonlinearity (DNL) are important metrics influencing the time linearity. Thus, several schemes have been presented to correct INL or DNL values by using time histograms [14,[26][27][28][29].…”