A 192 x 128 pixel single photon avalanche diode (SPAD) time-resolved single photon counting (TCPSC) image sensor is implemented in STMicroelectronics 40nm CMOS technology. The 13 % fill-factor, 18.4 x 9.2 m pixel contains a 33 ps resolution, 135 ns full-scale, 12-bit time to digital converter (TDC) with 0.9 LSB differential and 5.64 LSB integral nonlinearity (DNL/INL). The sensor achieves a mean 219 ps full-width half maximum (FWHM) impulse response function (IRF) and is operable at up to 18.6 kfps. Cylindrical microlenses with a concentration factor of 3.25 increase the fill-factor to 42 %. The median dark count rate (DCR) is 25 Hz at 1.5 V excess bias. Fluorescence lifetime imaging microscopy (FLIM) results are presented.Index Terms-single photon avalanche diode, CMOS image sensor, fluorescence lifetime imaging microscopy. laser ranging.

This paper presents low nonlinearity, compact, and multichannel time-to-digital converters (TDC) in Xilinx 28 nm Virtex 7 and 20 nm UltraScale field-programmable gate arrays (FPGAs). The proposed TDCs integrate several innovative methods that we have developed: 1) the subtapped delay line averaging topology; 2) tap timing tests; 3) a direct compensation architecture; and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25% of the logic resources. The achieved least significant bit (LSB) is 10.5 ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [-0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [-0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [-0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [-0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA. Index Terms-Carry chains, field-programmable gate arrays (FPGA), multichannel TDCs, time-of-flight, time-todigital converters (TDC).

No abstract

A 192 x 128 pixel single photon avalanche diode (SPAD) time-resolved single photon counting (TCPSC) image sensor is implemented in STMicroelectronics 40nm CMOS technology. The 13 % fill-factor, 18.4 x 9.2 µm pixel contains a 33 ps resolution, 135 ns full-scale, 12-bit time to digital converter (TDC) with 0.9 LSB differential and 8.7 LSB integral nonlinearity (DNL/INL). The sensor achieves a mean 219 ps fullwidth half maximum (FWHM) impulse response function (IRF) and a 5 mW core power consumption and is operable at up to 18.6 kfps. Cylindrical microlenses with a concentration factor of 3.15 increase the fill-factor to 41%. The median dark count rate (DCR) is 25 Hz at 1.5 V excess bias. Fluorescence lifetime imaging (FLIM) results are presented. I.

No abstract