A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

Kang, Seong-Hoon; Cho, Woo Yeong; Cho, Beak-Hyung; Lee, Kwang-Jin; Lee, Chang‐Soo; Oh, Hansu; Choi, Byoungdeog; Wang, Qi; Kim, Hye-Jin; Park, Mu-Hui; Ro, Yu Hwan; Kim, Su Yeon; Ha, Choong-Duk; Kim, Ki-Sung; Kim, Youngran; Kim, Du-Eung; Kwak, Choong-Keun; Byun, Hyun-Geun; Jeong, Gitae; Jeong, Hae-Yong; Kim, Kinam; Shin, Younghak

doi:10.1109/jssc.2006.888349

Cited by 122 publications

(53 citation statements)

References 6 publications

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“…As discussed previously, writing a 0 requires a large current to heat GST. The Dickson charge pump is widely used in PCM chips to provide electric current to the write driver with low power efficiency [6]. The noise on the power line prevents the charge pump from providing a high level of instantaneous current needed for write [6].…”

Section: B Pcm Power Delivery Constrainsmentioning

confidence: 99%

“…The Dickson charge pump is widely used in PCM chips to provide electric current to the write driver with low power efficiency [6]. The noise on the power line prevents the charge pump from providing a high level of instantaneous current needed for write [6]. In addition, the noise constraints of charge pump also limit the number of cells that can be concurrently written to 2, 4, and 8 typically in a chip [6].…”

Section: B Pcm Power Delivery Constrainsmentioning

confidence: 99%

“…Similar to DRAM, a high storage density PCM array also has multiple subarrays for two important reasons [2], [6].…”

Section: Fig 2 Subarray In a Bankmentioning

confidence: 99%

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Exploiting Subarrays inside a Bank to Improve Phase Change Memory Performance

Yue

Zhu

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-Enabling subarrays reduces memory latency by allowing concurrent accesses to different subarrays within the same bank in the DRAM system. However, this technology has great challenges in the PCM system since an on-going write cannot overlap with other accesses due to large electric current draw for writes. This paper proposes two new mechanisms (PASAK and WAVAK) that leverage subarray-level parallelism to enable a bank to serve a write and multiple reads in parallel without violating power constraints. PASAK exploits the electric current difference between writing a bit 0 and a bit 1, and provides a new power allocation strategy that better utilizes the power budget to mitigate the performance degradation due to bank conflicts. WAVAK adds a simple coding method that inverts all bits to be written if there are more zeros than ones, with a goal to reduce electric current for writes and create larger power surplus to serve more reads if there is no subarray conflict. Experimental results under 4-cores SPEC CPU 2006 workloads show that our proposed mechanisms can reduce memory latency by 68.7% and running time by 34.8% on average, comparing with the standard PCM system. In addition, our mechanisms outperform Flip-N-Write 14.6% in latency and 8.5% in running time on average.

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Section: B Pcm Power Delivery Constrainsmentioning

confidence: 99%

Section: B Pcm Power Delivery Constrainsmentioning

confidence: 99%

See 1 more Smart Citation

Exploiting Subarrays inside a Bank to Improve Phase Change Memory Performance

Yue

Zhu

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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“…Resistive memories such as PRAMs has been studied for many years because it has faster read and write access times and better scalability than FLASH memories [1,2,3,4,5]. Among various resistive memories, the diode-switch PRAM is currently replacing the MOS-switch one due to its small cell size without suffering loss of current driving capability [2].…”

Section: Introductionmentioning

confidence: 99%

“…In the MOS-switch PRAM, the sensing node is discharged to 0 V before read operation starting [1]. Once the MOS-switch PRAM cell is read, a fixed amount of read current flows through the cell resistance and this current is converted to a voltage according to the stored cell resistance.…”

Section: Introductionmentioning

confidence: 99%

Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs

Bong

Min

2009

IEICE Electron. Express

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Abstract:In this letter, a new read circuit with self-adjusted column pulse width is proposed for low-power applications of resistive memories. In the conventional read circuit, its column pulse width is determined by the worst-case value of the cell resistance variations thereby the pulse width being longer than required when the resistance variations are not in the worst case. In this paper, to alleviate power loss due to this long column pulse width, the column pulse width is selfadjusted according to the resistance variations thus unnecessary power loss being able to be reduced significantly. The power consumption during the read is expected to be less by 28.6% than the conventional circuit when the SET resistance is its mean value as large as 2 kΩ. The Monte Carlo simulation also shows that the power consumption of the proposed circuit is reduced by 25% in average than the conventional.

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Design Technology of Stacked‐Type Chain PRAM

Kato

Watanabe

2015

Elect Comm in Japan

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SUMMARYA stacked-type chain PRAM that can result in lower cost than flash memory has been proposed. The newly proposed memory cell uses a PCM for data storage and an MOS transistor connected in parallel. This memory cell is connected in series to realize the chain structure. The cell structure, the design method for realizing stable read and write operation, and the core circuit for the stacked-type chain PRAM are described. The newly proposed memory cell has been designed to use BiCS (Bit Cost Scalable) process technology in order to achieve low-cost memory. The design of the resistance of the PCM and the pass transistor is a key issue for realizing stable operation. To design the row decoder, the circuit concept of stacked ferroelectric RAM (FeRAM) with an NAND structure cell has been successfully adopted with SGT. The newly proposed stacked-type chain PRAM is a promising candidate for realizing high-speed and low-power future nonvolatile semiconductor memory. C⃝ 2015 Wiley Periodicals, Inc. Electron Comm Jpn, 98(2): 32-42, 2015; Published online in Wiley Online Library (wileyonlinelibrary.com).

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A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

Cited by 122 publications

References 6 publications

Exploiting Subarrays inside a Bank to Improve Phase Change Memory Performance

Exploiting Subarrays inside a Bank to Improve Phase Change Memory Performance

Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs

Design Technology of Stacked‐Type Chain PRAM

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