The analysis of bit cost and the performance of stacked type chain PRAM bas been newly described. Using the optimized number of layer the bit cost of stacked type chain PRAM with stacked horizontal plane structure or BiCS type structure can be reduced compared with that of 1 layer NAND flash memory. The smallest bit cost of BiCS type structure is as small as 0.08 of 1 layer NAND flash memory using the optimized number of layer of 64. The delay time of WL and BL of stacked type chain PRAM with BiCS type structure has been estimated. Using the optimized number layer of 64 for realizing smallest bit cost the delay time of WL and BL are less than 5ns which is competitive to DRAM. Because of estimated high speed characteristics and low bit cost, the chain PRAM wth BiCS type structure is the promising candidate for replacing DRAM and NAND flash memory.

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SUMMARYA stacked-type chain PRAM that can result in lower cost than flash memory has been proposed. The newly proposed memory cell uses a PCM for data storage and an MOS transistor connected in parallel. This memory cell is connected in series to realize the chain structure. The cell structure, the design method for realizing stable read and write operation, and the core circuit for the stacked-type chain PRAM are described. The newly proposed memory cell has been designed to use BiCS (Bit Cost Scalable) process technology in order to achieve low-cost memory. The design of the resistance of the PCM and the pass transistor is a key issue for realizing stable operation. To design the row decoder, the circuit concept of stacked ferroelectric RAM (FeRAM) with an NAND structure cell has been successfully adopted with SGT. The newly proposed stacked-type chain PRAM is a promising candidate for realizing high-speed and low-power future nonvolatile semiconductor memory. C⃝ 2015 Wiley Periodicals, Inc. Electron Comm Jpn, 98(2): 32-42, 2015; Published online in Wiley Online Library (wileyonlinelibrary.com).