Design Technology of Stacked Type Chain PRAM

Kato, Sho; Watanabe, Soichi

doi:10.1541/ieejeiss.133.937

Cited by 2 publications

(5 citation statements)

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“…And also, R P must be small enough for realizing high speed operation. The minimum value of R P is about 1.2KΩ in the case of 32-50nm design rule [7]. As a result, the total of resistance of BL becomes 1.2 KΩ *(N-1)+2.6 KΩ.…”

Section: Analysis Of Access Time Of Stacked Type Chain Prammentioning

confidence: 96%

“…Therefore, if the number of N is large enough, the bit cost with stacked horizontal plane structure can be reduced compared with that with one layer horizontal plane structure. The cross sectional view of chain PRAM with BiCS type structure is shown in Fig.3 (A) [7]. The equivalent circuit is shown in Fig.3 (B).…”

Section: Analysis Of Bit Cost Of Stacked Type Chain Prammentioning

confidence: 99%

“…In the case of chain structure there is a relationship between the resistance of pass transistor R P and the resistance of PCM R L . For realizing stable read write operation R P / R L should be smaller than 0.46 [7]. And also, R P must be small enough for realizing high speed operation.…”

Section: Analysis Of Access Time Of Stacked Type Chain Prammentioning

confidence: 99%

“…We call this as one layer horizontal plane structure. For realizing lower bit cost than one layer horizontal plane structure, stacking of one layer horizontal plane structure [6] (stacked horizontal plane structure) and BiCS (Bit Cost Scalable) type structure [7] [8] has been proposed. In this BiCS type structure a chain structure is fabricated in a vertical to the horizontal plane.…”

Section: Introductionmentioning

confidence: 99%

“…In this BiCS type structure a chain structure is fabricated in a vertical to the horizontal plane. In the previous works, the fabrication method [3][7] [8] and the memory cell design inherent to the chain structure [7] have been described. However, the analysis of bit cost and the performance (the access time) has not been reported.…”

Section: Introductionmentioning

confidence: 99%

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Analysis of bit cost and performance for stacked type chain PRAM

Kato¹,

Watanabe²

2013

ces

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The analysis of bit cost and the performance of stacked type chain PRAM bas been newly described. Using the optimized number of layer the bit cost of stacked type chain PRAM with stacked horizontal plane structure or BiCS type structure can be reduced compared with that of 1 layer NAND flash memory. The smallest bit cost of BiCS type structure is as small as 0.08 of 1 layer NAND flash memory using the optimized number of layer of 64. The delay time of WL and BL of stacked type chain PRAM with BiCS type structure has been estimated. Using the optimized number layer of 64 for realizing smallest bit cost the delay time of WL and BL are less than 5ns which is competitive to DRAM. Because of estimated high speed characteristics and low bit cost, the chain PRAM wth BiCS type structure is the promising candidate for replacing DRAM and NAND flash memory.

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Section: Analysis Of Access Time Of Stacked Type Chain Prammentioning

confidence: 96%

Section: Analysis Of Bit Cost Of Stacked Type Chain Prammentioning

confidence: 99%

Section: Analysis Of Access Time Of Stacked Type Chain Prammentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations