A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

Lee, Jinhyung; Lee, Kwang-Ho; Kim, Hyo-Jun; Kim, Byung-Min; Park, Kwanseo; Jeong, Deog‐Kyoon

doi:10.1109/jssc.2020.2987690

Cited by 42 publications

(10 citation statements)

References 27 publications

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“…Content may change prior to final publication. TCAS-I 17 [10] TCAS-II 18 [7] ISSCC 19 [13] JSSC 20 [11] This Work…”

Section: Discussionmentioning

confidence: 99%

“…However, such an analog method is vulnerable to PVT variations and not scalable to the CMOS process shrink. In [11], the adaptation based on the SS-LMS algorithm is adopted to both equalizers. However, the equalizer adaptation based on SS-LMS algorithm requires an additional power-hungry error sampler.…”

Section: Introductionmentioning

confidence: 99%

“…A clock and data recovery (CDR) is also an important option to achieve a low BER in the high-speed receivers. In most cases, the equalizer adaptation and clock recovery loop are implemented separately [10]- [11], as shown in Fig. 1(a).…”

Section: Introductionmentioning

confidence: 99%

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A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector

Choi

Hwang²,

Lee

et al. 2021

IEEE Access

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This paper presents an area-and energy-efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output clock of a digitally controlled oscillator (DCO) for both the equalizer adaptation and clock recovery loop, the proposed adaptive equalizer is combined with the CDR by sharing its adaptation loop including a sub-sampling phase detector (SSPD) and a digital logic circuit. Consequently, the active area and power dissipation for the adaptive equalizer are reduced. Furthermore, the SEC is proposed to improve the high-frequency jitter tolerance of the CDR. The SEC detects bit errors by observing the comparator decision and corrects the errors without any data encoding or complicate circuits. The out-of-band jitter tolerance is improved by 22.6% at 100 MHz for 17.2-dB loss channel with <10 -12 biterror rate (BER) with the proposed SEC. The SEC is applicable to various receivers with compact design at a low cost. The prototype receiver consumes 23.9 mW at 14-Gb/s and occupies 0.007 mm 2 in a 28-nm CMOS technology.INDEX TERMS Adaptive equalizer, clock and data recovery (CDR), continuous-time linear equalizer (CTLE), decision feedback equalizer (DFE), jitter tolerance, receiver, self-error corrector (SEC), subsampling.

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“…Content may change prior to final publication. TCAS-I 17 [10] TCAS-II 18 [7] ISSCC 19 [13] JSSC 20 [11] This Work…”

Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector

Choi

Hwang²,

Lee

et al. 2021

IEEE Access

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“…Common equalization techniques in high-speed serial links can be divided into liner equalizers (LE) and decision feedback equalizer (DFE) [5,6,7,8,9]. LE uses the frequency characteristics of the adjustable filter to compensate the channel loss, but for high-speed (> 5 Gbps) serial link, since the signal jitter (such as ISI related deterministic jitter) may exceed a symbol interval (UI), using LE alone is no longer applicable [10,11,12,13]. On the other hand, LE amplifies the noise and signal together, which does not improve the BER performance of the communication system [14,15,16].…”

Section: Introductionmentioning

confidence: 99%

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

Zhu

Chu

2023

IEICE Electron. Express

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This work proposes a RX front-end structure, which is used for channel equalization of 25 Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19 dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005 mm 2 designed in 65 nm CMOS, the power consumption of which is 96 mW under 1.2 V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35 dB at 12.5 GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171 mV and 0.61 UI at the BER of 10 −12 , respectively.

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“…As the data rate increases in a high-speed serial link demand for high speed chip-to-chip data communication links. [1][2] [3] However, due to skin effects and dielectric losses in the channel, the high-speed serial signal is severely attenuated and distorted after passing through the lossy channel. [4] The solution is to add separate equalization circuits at the transmitter and receiver ends to compensate for the high frequency loss of the channel and to improve data integrity.…”

Section: Introductionmentioning

confidence: 99%

A 20Gb/s Two-Stage Active Inductor CTLE in 28-nm CMOS

Zhang

Wang

et al. 2022

Preprint

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This paper presents a continuous-time linear equalizer (CTLE) with an active inductor load simultaneously connected in parallel to low frequency branch. The equalizer uses two-stage CTLE, the first stage compensating for high-frequency (HF) attenuation and the second stage equalizer compensates medium-frequency (MF) and HF by parallel low-frequency branches. The MF stage is used for the long-tail Intern symbol interference (ISI) equalization to minimize residual ISI. Equalizer with voltage control capacitor to configure the distribution of zero poles, for the HF has a configurable range of 0.5dB.The low-frequency gain can be configured by changing the load current of the active inductor to reduce the effect of parasitic resistance on the layout. The layout size is 5.9um*6um based on a 28nm CMOS process. The post layout results show that the equalizer has a maximum compensation capability of 10.37dB at a rate of 20Gb/s with an eye width of 0.85UI.

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A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

Cited by 42 publications

References 27 publications

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

A 20Gb/s Two-Stage Active Inductor CTLE in 28-nm CMOS

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