A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

Takao, Yoshihiro; Kawamura, Hiroshi; Mitani, J.; Kotani, Yoshiyuki; Yamaguchi, S.; Yoshie, K.; Sukegawa, K.; Naori, Nobuhisa; Asai, Satoru; Kawano, Michiari; Nagano, Takashi; Yamamura, I.; Uematsu, Masaya; Nishida, Naoki; Kadomura, S.

doi:10.1016/s0026-2714(01)00233-5

Cited by 5 publications

(1 citation statement)

References 16 publications

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“…interconnection, where the interconnect length was 500 grids and a grid was equal to 0.4 µm, showed a 70% improvement compared to 0.18-µm CMOS technology with copper/FSG interconnection using this technology. 18,19) The simulated line capacitance in the M2 structure (k = 2.7, 4.1, and 7.0, respectively, for SiLK T.M. , SiO 2 , and SiN) was 160-170 fF/mm, which was close to the measured value.…”

Section: Interconnect Performancesupporting

confidence: 75%

Integration of High Performance CMOS Logic LSI by Applying Cu Wiring to SiLKT.M./SiO2 Hybrid Structure

et al. 2002

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This paper describes a 0.13-µm CMOS made by using highly reliable copper and SiLK T.M. (DOW CHEMICAL) interconnection technologies. We propose a hybrid interlayer structure with SiLK T.M. at the trench level and SiO 2 at the via level to improve electrical properties, mechanical strength, and reliability. Using these technologies, we made a fully functional 1.5-Mbit SRAM macro and investigated the reliability of its copper wiring in terms of electromigration.

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Section: Interconnect Performancesupporting

confidence: 75%

Integration of High Performance CMOS Logic LSI by Applying Cu Wiring to SiLKT.M./SiO2 Hybrid Structure

et al. 2002

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Mechanical and tribological properties of interlayer films for the damascene-Cu chemical-mechanical planarization process

Sikder

Kumar

2002

Journal of Elec Materi

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Chemical-mechanical planarization (CMP) is a key technology for the Cu-damascene wiring process in integrated circuit (IC) manufacturing. 1-3 Chemical-mechanical planarization (CMP) is important for the semiconductor industry in manufacturing six or more levels of multilevel interconnects with critical dimensions of sub-one-tenth micron. In general, each silicon wafer is exposed to 15 or more CMP steps prior to final device assembly. During CMP, the wafer is pressed face down against a rotating polishing pad, while a chemically and physically active slurry planarizes the wafer. As wafer size grows, device sizes shrink, process requirements become more rigorous, and the uniformity within die/wafer and the CMP removal rate become a greater concern. Often, a change in slurry or operating conditions leads to conflicting results. Hence, there is a need for a better understanding of all the complex tribological interactions among slurry, polishing pad, wafer, and pad conditioner. Fundamental tribological studies and characterization of consumables allow the optimization of the pad design, material selection, process pressure, orbital and linear speed, chemical solution, within-wafer uniformity, and local planarization. [4][5][6][7][8] With the shrinkage of the device dimension and the increase in device density, low dielectric-constant (low-k) materials have attracted enormous interest because they can minimize the propagation delay, interconnect capacitance, and cross talk between signal lines for deep submicron ICs. 9-11 Various low-k materials are emerging as potential replacements for SiO 2 . In addition, electrically more conductive Cu has replaced Al metallization to reduce the overall RC (resistance-capacitance) delay. 12,13 Although the device performance will improve by using low (k Ͻ 3) films along with Cu metallization, several problems need to be solved from

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Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

Ong

Kripesh

et al. 2010

Microelectronics Reliability

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A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

Cited by 5 publications

References 16 publications

Integration of High Performance CMOS Logic LSI by Applying Cu Wiring to SiLK<SUP>T.M.</SUP>/SiO<SUB>2</SUB> Hybrid Structure

Integration of High Performance CMOS Logic LSI by Applying Cu Wiring to SiLK<SUP>T.M.</SUP>/SiO<SUB>2</SUB> Hybrid Structure

Mechanical and tribological properties of interlayer films for the damascene-Cu chemical-mechanical planarization process

Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

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