This paper describes a 0.11 p m CMOS technology with high-reliable copper and very-low-k (VLK) (kc2.7) interconnects for high performance and low power applications. Aggressive design rules, 0.11 p m gate transistor, and 2.2 p mz 6T-SRAh4 cell are realized by using KrF 248nm lithography, opticalproximity-effect correction (OPC), and gate-shrink techniques. Drain current of 0.63mA/ p m and 0.281nN p m are realized for nMOSFET and pMOSFET with 0.11 p m gate, respectively. Propagation delay of 2-input NAND with the copperlhybrid VLK interconnects is estimated. The delay is improved by more than 70%, compared to 0.18 fi m CMOS technology with copper/FSG interconnects.

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We investigated the dependence of temperature uniformity dufi ng millisecond annealing (MSA) on the pattern density and its effect on device characteristics and static random access memory (SRAM) yields with 45-nm node technology. By comparing flash lamp annealing (FLA) and laser spike annealing (LSA), we found FLA was diffi cult to use in our multiple MSA scheme without absorbing layers because of its high temperature uniformity sensitivity to pattern density. LSA was found to be more promising due to its lower sensitivity to pattern density and higher potential for enhancing performance. We also found hot spots were generated during LSA; however, these can easily be avoided by introducing LSA-friendly design rules.

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