A 0.12–0.4 V, Versatile 3-Transistor CMOS Voltage Reference for Ultra-Low Power Systems

Summary A high‐order curvature‐compensated subthreshold voltage reference is proposed in this paper. The proposed curvature‐compensated voltage reference consists of two supply‐independent first‐order voltage references and a curvature compensation circuit. The supply‐independent first‐order voltage reference uses a negative feedback loop which improves the line sensitivity and eliminates the demand of operational amplifier, whereas the curvature compensation circuit provides high‐order temperature‐compensated output reference voltage. The proposed curvature‐compensated voltage reference provides an output reference voltage of 118.54 mV with a temperature coefficient of 21.5 ppm/°C over a wide temperature range of −60°C to 120°C. The power supply rejection ratio and line sensitivity are observed as −68.64 dB (for the frequency range of 1 Hz to 100 Hz) and 0.035%/V (for the supply voltage varies from 0.85 V to 2.5 V), respectively. The values of output noise at the frequencies of 1 kHz and 10 kHz without using any capacitive filter are obtained as 179.13 nV/ √ Hz and 123.87 nV/ √ Hz, respectively.

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“…The FOM 1 is expressed in terms of temperature range ( T max − T min ), temperature coefficient (TC), power, and area as 49,50

{FOM}_{1} = \frac{{((), T_{\max} - T_{\min})}^{2}}{TC \times Power \times Area} \times \frac{1}{10^{21}} .

…”

Section: Simulation Resultsmentioning

confidence: 99%

Low temperature coefficient and low line sensitivity subthreshold curvature‐compensated voltage reference

Thakur

Pandey

Kumar

2020

Circuit Theory & Apps

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“…A precise and stable voltage reference (VR), insensitive to temperature and supply voltage variations, is essential in most systems‐on‐chips applications. In view of the increasing demand for ultra‐low‐power (ULP) systems, such as energy harvesters and a wide variety of Internet‐of‐Thing devices, a number of VRs consuming from nanowatt down to femtowatt have been widely reported in recent years [1–4 ]. Scaling down below deep nanometre nodes (

< 65 nm

) creates further challenges, since the direct tunnelling gate leakage currents have substantial influence on design [5 ].…”

Section: Introductionmentioning

confidence: 99%

“…At ULP levels and temperatures below

0 ° C

, the impact of such leakage is more significant in view of the fact that sub‐threshold current achieves a similar order. The traditional 3‐transistor (3 T) self‐regulated VR uses the sub‐threshold leakage current for self‐bias functionality [2, 4 ]. The high gate leakage in deep nanometre processes, in particular the 28 nm ultra‐thin buried oxide (UTBB) fully depleted silicon‐on‐insulator (FD‐SOI) CMOS evaluated in this work, causes significant errors in traditional 3 T VRs, and hence additional technique are required for proper operation of the VR.…”

Section: Introductionmentioning

confidence: 99%

Gate leakage compensation technique for self‐cascode based voltage references

Olivera

Petraglia

2020

Electron. lett.

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This communication describes a gate leakage compensation technique to ensure wide‐temperature operation and wide‐supply regulation of traditional self‐cascode based voltage references in deep nanometre nodes ( <65 thinmathspacenm ). Extensive simulations in 28 nm ultra‐thin buried oxide fully depleted silicon‐on‐insulator CMOS process show that the proposed 4‐transistor topology can operate down to 0.2 V, generating a reference voltage of 98.2 mV with mean and best temperature coefficients of 68.9 and 18.2 thinmathspaceppm/°C, respectively, from −40 to 120 thinmathspace°C.

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“…Introduction: Voltage and current references operating at nano-watt power level are highly demanded for battery-powered Internetof-Things systems where the static power budget is extremely limited [1][2][3]. These circuits are, conventionally, realised using the MOSFETs biased in subthreshold regime.…”

mentioning

confidence: 99%

“…The threshold voltages V TH1 and V TH2 of M 1 and M 2 are both complementary-to-absolute-temperature (CTAT), and can be characterised using the following linear expression [1][2][3][4]:…”

mentioning

confidence: 99%

Self‐biased nano‐power four‐transistor current and voltage reference with a single resistor

Aminzadeh

2020

Electron. lett.

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A generic nano‐power voltage and current reference topology, which takes advantage of the unequal threshold voltage (VnormalTH) of two MOSFETs in subthreshold region, is developed to provide reliable bias and reference signals for the analogue integrated blocks used in the Internet‐of‐Things applications. The new architecture is a self‐powered four‐transistor topology with a single temperature‐insensitive resistor, generating both temperature‐independent voltage and current without any operational amplifier or bias network. Instead, the resistor defines the absolute value of the current reference (InormalREF) which supplies the core devices. The circuit is designed and simulated for a target current reference of 7.50 nA in 0.18 µm CMOS process, and achieves a worst‐case temperature coefficient (TC) of 59.47 ppm/°C over a temperature range from −40 to 125°C and 1.8 V voltage supply. The average voltage reference (VnormalREF) is 346 mV, and the worst‐case TC of different corners is 21.98 ppm/°C. The nominal current consumption is twice the InormalREF (15 nA) regardless of the supply and temperature, and can be scaled down by reducing the desired current reference.

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A 0.12–0.4 V, Versatile 3-Transistor CMOS Voltage Reference for Ultra-Low Power Systems

Cited by 48 publications

References 18 publications

Low temperature coefficient and low line sensitivity subthreshold curvature‐compensated voltage reference

Low temperature coefficient and low line sensitivity subthreshold curvature‐compensated voltage reference

Gate leakage compensation technique for self‐cascode based voltage references

Self‐biased nano‐power four‐transistor current and voltage reference with a single resistor

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