A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

Rahimunnisa, K.; Karthigaikumar, P.; Kirubavathy, J.; Jayakumar, Jaikishan; Kumar, Satyendra

doi:10.1080/00207217.2013.775626

Cited by 6 publications

(2 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Moreover in [19] a parallel sub-pipelined architecture is introduced for high security applications producing high throughput. In [20] the architecture for both encryption and decryption using AES is designed by incorporating folded architecture with parallel architecture to increase the throughput and reduce the power consumption. In [21] a parallel sub-pipelined architecture is introduced for AES algorithm.…”

Section: Related Workmentioning

confidence: 99%

FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

2020

Self Cite

View full text Add to dashboard Cite

Advanced Encryption Standard (AES) is a thriving cryptographic algorithm that can be utilized to guarantee security in electronic information. It remains to uphold to be resistive from most of the attacks. In this work, AES-128 encryption iterative architecture is designed to achieve minimum area and less hardware utilization. Reduced area is attained by introducing a renovated S-box structure into the AES algorithm. Furthermore, hardware utilization is minimized by incorporating the Vedic multiplier in the Mix column transformation of the AES Encryption process. The proposed encryption architecture is of 128-bit size and was executed on the Xilinx Spartan FPGA series, namely, Spartan 3, Virtex-4 and Virtex-5 devices. The optimization result exhibits that the proposed S-box technique has a smaller area than other existing conventional works.

show abstract

Section: Related Workmentioning

confidence: 99%

FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

2020

Self Cite

View full text Add to dashboard Cite

show abstract

“…This method reduces the time consumption of round function significantly and is the fastest non-parallelised software implementation which has been adopted by many security systems like OpenSSL (Viega et al, 2002). Moreover, the LUT-based AES software implementations are more applicable than the ones based on hardware accelerators (Rahimunnisa et al, 2014;Abdellatif et al, 2014;Chang et al, 2013;Swankoski et al, 2005) or the ones based on instruction set extension (Rott, 2012;Lee and Chen, 2010;Yumbul et al, 2014) due to its' hardware-independency characteristic.…”

Section: Introductionmentioning

confidence: 99%

Access-driven cache attack resistant and fast AES implementation

Wan

Luo

et al. 2018

IJES

View full text Add to dashboard Cite

Contents:IJES is a refereed international journal providing an international forum to report, discuss and exchange experimental or theoretical results, novel designs, work-in-progress, experience, case studies, and trend-setting ideas. Papers should be of a quality that represents the latest advances in embedded systems in time-to-market, cost, code size, weight, testability, power, real-time behaviour, and stimulating future trends.

show abstract

Computational Approach for Securing Radiology-Diagnostic Data in Connected Health Network using High-Performance GPU-Accelerated AES

Adeshina

Hashim

2016

Interdiscip Sci Comput Life Sci

View full text Add to dashboard Cite

Diagnostic radiology is a core and integral part of modern medicine, paving ways for the primary care physicians in the disease diagnoses, treatments and therapy managements. Obviously, all recent standard healthcare procedures have immensely benefitted from the contemporary information technology revolutions, apparently revolutionizing those approaches to acquiring, storing and sharing of diagnostic data for efficient and timely diagnosis of diseases. Connected health network was introduced as an alternative to the ageing traditional concept in healthcare system, improving hospital-physician connectivity and clinical collaborations. Undoubtedly, the modern medicinal approach has drastically improved healthcare but at the expense of high computational cost and possible breach of diagnosis privacy. Consequently, a number of cryptographical techniques are recently being applied to clinical applications, but the challenges of not being able to successfully encrypt both the image and the textual data persist. Furthermore, processing time of encryption-decryption of medical datasets, within a considerable lower computational cost without jeopardizing the required security strength of the encryption algorithm, still remains as an outstanding issue. This study proposes a secured radiology-diagnostic data framework for connected health network using high-performance GPU-accelerated Advanced Encryption Standard. The study was evaluated with radiology image datasets consisting of brain MR and CT datasets obtained from the department of Surgery, University of North Carolina, USA, and the Swedish National Infrastructure for Computing. Sample patients' notes from the University of North Carolina, School of medicine at Chapel Hill were also used to evaluate the framework for its strength in encrypting-decrypting textual data in the form of medical report. Significantly, the framework is not only able to accurately encrypt and decrypt medical image datasets, but it also successfully encrypts and decrypts textual data in Microsoft Word document, Microsoft Excel and Portable Document Formats which are the conventional format of documenting medical records. Interestingly, the entire encryption and decryption procedures were achieved at a lower computational cost using regular hardware and software resources without compromising neither the quality of the decrypted data nor the security level of the algorithms.

show abstract

A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

Cited by 6 publications

References 14 publications

FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications

Access-driven cache attack resistant and fast AES implementation

Computational Approach for Securing Radiology-Diagnostic Data in Connected Health Network using High-Performance GPU-Accelerated AES

Contact Info

Product

Resources

About