This paper presents high throughput architecture for the hardware implementation of Advanced Encryption Standard algorithm. Advanced Encryption Standard is the industry standard crypto algorithm for encryption and is used for protecting secret information. This work is mainly targeted for low‐cost embedded applications. This paper introduces parallel operation in the folded architecture to obtain better throughput. The design is coded in Very High‐speed Integrated Circuit Hardware Description Language. Timing simulation is performed to verify the functionality of the designed circuit. The proposed structure is implemented in Virtex‐6 XC6VLX75T FPGA device. This work gives a high throughput of 37.1 Gb/s with a maximum frequency of 505.5 MHz, which is 20% higher than the maximum throughput reported in the literature. Copyright © 2012 John Wiley & Sons, Ltd.

As the technology is growing day by day, information security plays a very important role in our lives. In order to protect the information, several cryptographic algorithms have been proposed. The aim of this paper is to present an effective Advanced Encryption Standard (AES) architecture to achieve high throughput for security applications. The Parallel Sub-Pipelined architecture (PSP) is proposed in order to obtain high throughput. The proposed architecture is also compared with loop unrolled, pipelined, sub-pipelined, parallel and parallel pipelined architecture in terms of throughput. The AES algorithm using Parallel Sub-Pipelined architecture was prototyped in FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit).The proposed architecture yielded a throughput of 59.59 Gbps at a frequency of 450.045 MHz on FPGA Virtex XC6VLX75T which is higher than the throughput yielded in other architectures. In ASIC 0.13 µm technology, the proposed architecture yielded a throughput of 25.60 Gbps and in 0.18 µm, it yielded a throughput of 20.56 Gbps.

Advanced Encryption Standard has been built as the first choice for many cryptographic applications because of the high level of security. Data Security is primary concern for communication system. There are many methods to provide security data that is being communicated. However, security is assured irrespective of the hackers are from the noise. This paper presents a low power and low area design for the Advanced Encryption Standard based on an 8-bit data path. It has significant power-area-latency performance improvements over normal 128-bit data path AES. Such improvements are achieved by the use of resource sharing, simple compact memory architecture, Low Resource MixColumn Circuit, minimizing memory transfers and avoiding unnecessary switching activity. In addition to the performance requirements of the AES, it must be reliable against transient or permanent internal faults. The faults that accidently occur in the hardware implementations of the AES may cause erroneous output. At the end of the design, this paper presents parity-based fault detection scheme for high performance AES implementations.

A new architecture for encrypting and decrypting the confidential data using Advanced Encryption Standard algorithm is presented in this article. This structure combines the folded structure with parallel architecture to increase the throughput. The whole architecture achieved high throughput with less power. The proposed architecture is implemented in 0.13-µm Complementary metal-oxide-semiconductor (CMOS) technology. The proposed structure is compared with different existing structures, and from the result it is proved that the proposed structure gives higher throughput and less power compared to existing works.

No abstract