FPGA implementation of AES algorithm for high throughput using folded parallel architecture

Rahimunnisa, K.; Karthigaikumar, P.; Rasheed, Soumiya; Jayakumar, Jaikishan; Sureshkumar, Sridevi

doi:10.1002/sec.651

Cited by 38 publications

(18 citation statements)

References 29 publications

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“…García et al improved the clock cycle of a pipeline to decrease the delay. Rahimunnisa et al combined the features of the folding concept with parallel processing of Advanced Encryption Standard (AES) and obtained a throughput of 37.1 Gb/s. Hanindhito et al proposed two modular multiplication architectures based on an FPGA for 2048‐bit RSA and completed a decryption in 2.2 ms and 3.1 ms. Kawamoto et al proposed an approach for multiple‐length arithmetic operations on hardware and implemented a 2048‐bit RSA encryption with a 2.59‐ms delay on the Virtex‐6 FPGA.…”

Section: Related Workmentioning

confidence: 99%

A hybrid ARM‐FPGA cluster for cryptographic algorithm acceleration

Bai

Yang

Dai

et al. 2019

Concurrency and Computation

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Summary Clusters based on hybrid architectures combining ARM CPUs and FPGA fabric, such as the Xilinx Zynq SoC, not only are energy‐efficient platforms with strong processing power but also have the advantages of distributed computing systems balancing the workload between cores, processors, and nodes. This paper employs a 48‐node cluster infrastructure based on the Xilinx Zynq SoC to accelerate classical cryptographic algorithms, including hash functions, AES, and RSA. In this design, we leverage the flexibility of the software to implement node‐to‐node communication through the message passing interface (MPI), and we offload the compute‐intensive tasks to the FPGA to accelerate complex calculations with the parallelizability of specific reconfigurable coprocessors. In addition, we study several parallel cryptography optimizations based on FPGA to evaluate this cluster. Finally, using a comparison with a multi‐core desktop (Intel i7‐3770) and a many‐core server (288 cores), the efficiency of the implementations of the selected data encryption and decryption algorithms is presented to illustrate the performance of our system; we also gain up to 3.6× increase in energy efficiency.

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Section: Related Workmentioning

confidence: 99%

A hybrid ARM‐FPGA cluster for cryptographic algorithm acceleration

Bai

Yang

Dai

et al. 2019

Concurrency and Computation

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“…Cryptographic different approaches are demonstrated through [23][24][25][26][27][28][29] using Virtex 5 FPGA platform. While securing the data, with AES (Advanced Encryption Standard) as well as Data Decryption Systems Standard (DES) and Triple DES (TDES) using FPGA, different approaches are implemented to enhance the performance for secure communication.…”

Section: Vlsi Designmentioning

confidence: 99%

Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding

Desai

Mali

2018

VLSI Design

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Due to demand of information transfer through higher speed wireless communication network, it is time to think about security of important information to be transferred. Further, as these communication networks are part of open channel, to preserve the security of any Critical Information (CI) is really a challenging task in any real-time application. Data hiding techniques give more security and robustness of important CI against encryption or cryptographic software solutions. However, hardwired approach exhibits better solution not only in terms of reduction of complexity but also in terms of adaptive real-time output. This paper demonstrates frequency, Discrete Cosine Transform (DCT) domain Steganographic data hiding hardware solution for secret communication called Crypto-Stego-Real-Time (CSRT) System. The challenge is to design a secure algorithm keeping reliability of minimum distortion of original cover signal while embedding considerable amount of CI. Field Programmable Gate Array (FPGA) implementation shown in this paper is more secure, robust, and fast. Pipelining process while embedding enhances the speed of embedding, optimizes the memory utilization, and gives better Peak Signal to Noise Ratio (PSNR) and high robustness. Practically implemented hardware Steganographic solutions shown in this paper also give better performance than that of the current state-of-the-art hardware implementations.

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“…The logic resource utilization of the design is 303 slices. Another low cost AES implementation was proposed in [17]. This implementation proposed a high throughput design by the introduction of parallel operation in folded architecture.…”

Section: A Fpga Based Cryptosystemmentioning

confidence: 99%

A Low Cost FPGA based Cryptosystem Design for High Throughput Area Ratio

Ibrahim¹,

Ahmed²,

Aslam³

et al. 2017

ijacsa

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Abstract-Over many years, Field Programmable Gated Arrays (FPGA) have been used as a target device for various prototyping and cryptographic algorithm applications. Due to the parallel architecture of FPGAs, the flexibility of cryptographic algorithms can be exploited to achieve high throughputs at the expense of very low chip area. In this research, we propose a low cost FPGA based cryptosystem named as Secure Cipher for high throughput to area ratio. The proposed Secure Cipher is implemented using full loop unroll technique in order to exploit the parallelism of the proposed algorithm. The proposed cryptosystem implementation achieved a throughput of 4600Mbps for encryption. The logic resource utilization of this implementation is 802 logic elements(LE) which yields a throughput to area ratio of 5.735Mbps/LE.

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FPGA implementation of AES algorithm for high throughput using folded parallel architecture

Cited by 38 publications

References 29 publications

A hybrid ARM‐FPGA cluster for cryptographic algorithm acceleration

A hybrid ARM‐FPGA cluster for cryptographic algorithm acceleration

Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding

A Low Cost FPGA based Cryptosystem Design for High Throughput Area Ratio

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