A 0.13 μm CMOS platform with Cu/low-k interconnects for system on chip applications

Abstract

We describe an advanced 0.13pm CMOS technology platform optimized for density, performance, low power and analoghixed signal applications. Up to 8 levels of Copper interconnect with industries first true low-k dielectric (SiLK, k=2.7) [ l ] result in superior interconnect performance at aggressive pitches. A 2.28pm2 SRAM cell is manufactured with high yield by introducing elongated local interconnects on the contact level without increasing process complexity. Trench based embedded DRAM is offered for large area memory. Modular analog devices as well as passive components like resistors, MIM capacitors and intrinsic inductors are integrated. References(1) R. D. Goldblatt et al.: A High Performance 0.13 pm Copper BEOL Technology with Low-k Dielectric, IlTC 2000 (2) L.K. Han et al: A Modular 0.13pm BULK CMOS Technology for High performance and Low Power Applications, VLSI 2000, p. 12 (3) M. Armacost et al: A High Reliability Metal Insulator Metal Capacitor for 0,18 pm Copper Technology, IEDM 2000, p. 157 SiLK is a registixed trademark of The Dow Chemical Company 101 4-891 14-012-7/01 2001 Symposium on VLSI Technology Digest of Technical Papers

Compact quadrature receiver for 24 GHz radar applications in 0.13 µm CMOS

“…The circuit is realised in Infineon's 0.13 mm CMOS technology with six copper layers and a top aluminium level [6]. Only the analogue MIM capacitor option is used without additional RF-CMOS options such as a thick top metal or highresistivity substrate.…”

Merged power amplifier and mixer circuit topology for radar applications in CMOS

“…Furthermore, blocking capacitors have been added between VDD and GND to improve the power supply rejection . The circuit has been realized in Infineon's 0.13 urn technology described in [7]. The process offers 6 copper layers and 1.35 urn thick top aluminium layer.…”

A low power 24 GHz LNA in 0.13 μm CMOS

“…The die area including the pads is only 0.47 mm by 0.49 mm. The chip is processed in INFINEON's standard 0.13 µm CMOS technology with 6 Cu layers and one Al pad top level [7]. Only the analog MIM capacitor option is used without additional RF-CMOS options such as thick top metal or high-resistivity substrate.…”